Voltage random access memory (VRAM)

Abstract

An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.

1 . A method for storing a digital value in a memory location and causing a particular analog voltage to be output when that location is accessed, comprising
 providing, via a resistor ladder network coupled to at least one voltage reference, a plurality of analog reference voltages at a plurality of nodes therein; and   operating a compact array of a plurality of cells, each cell containing a storage device and a corresponding analog reference voltage switch, so that each storage device controls the state of the analog reference voltage located in the corresponding cell, and   coupling each such switch between a node in the resistor ladder network corresponding to a pre-selected one of the analog reference voltages, and an analog voltage output point.   
   
   
       2 . A method as in  claim 1  wherein the resistor ladder network is further for:
 connecting a first set of resistors connected in series to provide the set of reference analog voltages.   
   
   
       3 . A method as in  claim 2  additionally comprising
 connecting additional resistors arranged in parallel with one or more of the resistors in the first set to provide one or more fine reference analog voltages.   
   
   
       4 . A method as in  claim 1  wherein the storage device in at least one cell is for storing a single digital bit. 
   
   
       5 . A method as in  claim 4  wherein the storage device is a pair of cross coupled inverter gates. 
   
   
       6 . A method as in  claim 1  wherein multiple cells are connected to the same node in the resistor ladder network so as to be available to produce multiple analog output voltages. 
   
   
       7 . A method as in  claim 1  wherein each storage device in the array of cells is addressable. 
   
   
       8 . A method as in  claim 7  wherein each storage device in the array of cells is addressable by row and column decoders. 
   
   
       9 . A method as in  claim 1  additionally comprising:
 storing, in a first cell, digital information to produce a coarse analog voltage;   storing, in a second cell, digital information to produce a fine analog voltage; and   producing, via a difference amplifier connected to receive the coarse analog voltage and the fine analog voltage, the analog output as a voltage or current proportional to a difference there between.   
   
   
       10 . A method as in  claim 1  additionally comprising the step of providing a plurality of reference voltages in a charge to digital converter.