US2007220603A1PendingUtilityA1

Data Processing Method and Device

Assignee: OBERTHUR CARD SYST SAPriority: Aug 17, 2004Filed: Aug 12, 2005Published: Sep 20, 2007
Est. expiryAug 17, 2024(expired)· nominal 20-yr term from priority
G06F 21/552G06F 21/60
44
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Claims

Abstract

The invention concerns a data processing method comprising a step (E 308 ) which consists in verifying a criterion indicative of the normal running of the method and a step (E 320 ) which consists in processing performed in case of negative verification. The processing step (E 230 ) is separated from the verifying step (E 308 ) by an intermediate step (E 312 , E 314 ) of non-null duration. The intermediate step (E 312 , E 314 ) and/or the processing step (E 320 ) includes at least one action (E 314 ) performed in case of positive verification. The invention also concerns a corresponding device.

Claims

exact text as granted — not AI-modified
1 . Data processing method comprising: 
 a step of verification of a criterion indicative of the normal running of the method; and    a processing step (E 528 ) effected in the case of negative verification,    characterized in that, a first action (E 512 ) being effected in the case of positive verification, the processing step entails effecting at least one second action (E 528 ) having a first characteristic in common with the first action (E 512 ).    
   
   
       2 . Data processing method comprising: 
 a step (E 308 ; E 406 , E 410 , E 416 ) of verification of a criterion indicative of the normal running of the method; and    a processing step (E 320 ; E 458 ; E 528 ) effected in the case of negative verification,    wherein the processing step (E 320 ; E 458 ; E 528 ) is separated from the verification step (E 308 ; E 406 , E 410 , E 416 ) by an intermediate step (E 312 , E 314 ; E 450 , E 452 , E 454 , E 456 ; E 520 , E 522 , E 524 , E 526 ) of non-null duration, characterized in that, a first action (E 314 ; E 408 , E 412 , E 414 ; E 504 , E 506 , E 508 , E 510 ) being effected in the case of positive verification, the intermediate step entails effecting at least one second action (E 314 ; E 450 , E 454 , E 456 ; E 520 , E 522 , E 524 , E 528 ) having at least one first characteristic in common with the first action.    
   
   
       3 . Method according to  claim 1 , wherein the second action is different from the first action.  
   
   
       4 . Method according to  claim 2 , wherein, a third action (E 418 ; E 512 ) being effected in the case of positive verification, the processing step entails effecting at least one fourth action (E 458 ; E 528 ) having at least one second characteristic in common with the third action (E 418 ; E 512 ).  
   
   
       5 . Method according to  claim 1 , wherein, the method being implemented in electronic apparatus ( 10 ), the first or second common characteristic is the electrical consumption or the electromagnetic radiation of the apparatus generated by the first, respectively the third, action and by the second, respectively the fourth, action.  
   
   
       6 . Method according to  claim 1  any, wherein the first or second common characteristic is the number of instructions used in the first, respectively the third, action and in the second, respectively the fourth, action.  
   
   
       7 . Method according to  claim 1 , wherein the first or second common characteristic is the type of instruction used by the first, respectively the third, action and by the second, respectively the fourth, action.  
   
   
       8 . Method according to  claim 1  wherein the first or second common characteristic is the type of data processed by the first, respectively the third, action and by the second, respectively the fourth, action.  
   
   
       9 . Method according to  claim 1 , wherein the first, respectively the third, action entailing access to a first area of a memory, the second, respectively the fourth, action entails access to a second area of said memory different from the first area.  
   
   
       10 . Method according to  claim 1 , wherein the first or second common characteristic is communication with an external device.  
   
   
       11 . Method according to  claim 10 , wherein the external device is a cryptoprocessor.  
   
   
       12 . Method according to  claim 10 , wherein the external device is a memory ( 2 ,  6 ).  
   
   
       13 . Method according to  claim 10 , wherein the external device is a rewritable semiconductor memory ( 6 ).  
   
   
       14 . Method according to  claim 10 , wherein the external device is a user terminal.  
   
   
       15 . Method according to  claim 1 , wherein the first action entails a secure step.  
   
   
       16 . Method according to  claim 15 , wherein the secure step entails a cryptographic algorithm.  
   
   
       17 . Method according to  claim 1 , wherein the processing step (E 320 , E 528 ) entails writing blocking data into a physical memory ( 6 ).  
   
   
       18 . Method according to  claim 17 , wherein the writing (E 528 ) of blocking data is effected in accordance with a chronology identical to writing (E 512 ) data into the physical memory ( 6 ) in the case of normal running of the method.  
   
   
       19 . Method according to  claim 18 , wherein the data represents a pecuniary value.  
   
   
       20 . Method according to  claim 1 , wherein the criterion is negative if an erroneous signature is provided.  
   
   
       21 . Method according to  claim 1 , wherein the criterion is negative if an anomaly is detected.  
   
   
       22 . Method according to  claim 1 , wherein the criterion is negative if an attack is detected.  
   
   
       23 . Method according to  claim 1 , wherein the criterion is negative if a functional error is detected.  
   
   
       24 . Method according to  claim 2 , wherein the intermediate step entails at least one instruction determined during the execution of the method.  
   
   
       25 . Method according to  claim 1 , executed by a microprocessor ( 2 ) of a microcircuit card ( 10 ).  
   
   
       26 . Data processing device comprising: 
 means for verification of a criterion indicative of the normal operation of the device;    processing means used in the case of negative verification; and    separation means for separating the operation of the verification means from the operation of the processing means by a non-null duration,    characterized in that, first action means being used in the case of positive verification, the separation means have at least one first characteristic in common with the first action means.    
   
   
       27 . Device according to  claim 26 , wherein, second action means being used in the case of positive verification, the processing means have at least one second characteristic in common with the second action means.  
   
   
       28 . Data processing device comprising: 
 means for verification of a criterion indicative of the normal operation of the device; and    processing means used in the case of negative verification,    characterized in that, first action means being used in the case of positive verification, the processing means have at least one first characteristic in common with the first action means.    
   
   
       29 . Device according to  claim 26 , the device being a microcircuit card.

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