Methods of bridging lateral nanowires and device using same

Abstract

A semiconductor nanowire is grown laterally. A method of growing the nanowire forms a vertical surface on a substrate, and activates the vertical surface with a nanoparticle catalyst. A method of laterally bridging the nanowire grows the nanowire from the activated vertical surface to connect to an opposite vertical surface on the substrate. A method of connecting electrodes of a semiconductor device grows the nanowire from an activated device electrode to an opposing device electrode. A method of bridging semiconductor nanowires grows nanowires between an electrode pair in opposing lateral directions. A method of self-assembling the nanowire bridges the nanowire between an activated electrode pair. A method of controlling nanowire growth forms a surface irregularity in the vertical surface. An electronic device includes a laterally grown nano-scale interconnection.

1 - 43 . (canceled)  
     
     
         44 . An electronic device having a nano-scale interconnection comprising: 
 a pair of spaced apart semiconductor electrodes supported by a substrate, the electrodes each having an opposing vertical surface, the vertical surfaces being (111) semiconductor lattice planes, at least one of the vertical surfaces comprising a nanoparticle catalyst; and    a semiconductor nanowire laterally bridging the pair of electrodes between the opposing vertical surfaces, the laterally bridging semiconductor nanowire interconnecting the electrode pair.    
     
     
         45 . The electronic device of  claim 44 , wherein the substrate is a semiconductor-on-insulator substrate comprising a semiconductor layer on an insulator layer, the pair of electrodes being formed in the semiconductor layer, the semiconductor layer having a (110) crystal lattice plane that is oriented horizontally relative to the vertical surfaces.  
     
     
         46 . The electronic device of  claim 44 , wherein the bridging nanowire provides one or both of a mechanical connection and an electrical connection between the electrode pair.  
     
     
         47 . The electronic device of  claim 44 , wherein the vertical surfaces further comprise a surface irregularity in otherwise relatively smooth surfaces to control nanowire growth.  
     
     
         48 . The electronic device of  claim 44 , wherein a semiconductor material of the electrodes and a semiconductor material of the nanowire are either the same material or a different material.  
     
     
         49 . The electronic device of  claim 44 , wherein the semiconductor electrodes and the semiconductor nanowire comprise a semiconductor material independently selected from an element from group IV, two different elements from group IV, an element from group III with an element from group V, and an element from group II with an element from group VI.  
     
     
         50 . The electronic device of  claim 44 , wherein the semiconductor electrodes and the semiconductor nanowire comprise a semiconductor material independently selected from silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), aluminum nitride (AlN), zinc oxide (ZnO), and cadmium sulfide (CdS).  
     
     
         51 . The electronic device of  claim 44 , wherein the semiconductor electrodes comprises silicon, and wherein the semiconductor nanowire comprises a semiconductor material selected from silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), aluminum nitride (AlN), zinc oxide (ZnO), and cadmium sulfide (CdS).  
     
     
         52 . The electronic device of  claim 44 , further comprising an insulator layer sandwiched between the electrode pair and the substrate, the insulator layer being selected from silicon dioxide, silicon nitride and aluminum oxide.  
     
     
         53 . The electronic device of  claim 52 , further comprising an array of spaced apart devices, each device comprising a respective pair of the spaced apart electrodes and at least one nanowire interconnecting the respective electrode pair, the devices being isolated from the substrate by the insulator layer.  
     
     
         54 . An electronic device having a nano-scale interconnection comprising: 
 a pair of silicon electrodes supported by a substrate, the electrodes each having an opposing, spaced apart vertical surface, the vertical surfaces being (111) silicon lattice planes, the vertical surfaces comprising a nanoparticle catalyst; and    a silicon nanowire laterally bridging the pair of electrodes between the opposing vertical surfaces to interconnect the electrode pair.    
     
     
         55 . The electronic device of  claim 54 , wherein the substrate is a semiconductor-on-insulator substrate comprising a layer of silicon, the electrode pair being formed in the silicon layer.  
     
     
         56 - 60 . (canceled)