Digital communication system and method

Abstract

A digital communication system for transmitting and receiving video data signals and control data signals over a transmission line comprises an open-loop equalizer circuit and a control data extension circuit. The open-loop equalizer circuit is operable to receive video signals transmitted over the transmission line and output equalized video data signals. The control data extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the control data signal, and clamp the receive end of the transmission line during a negative transition of the control data signal.

1 . A digital communication system for transmitting and receiving video data signals and control data signals over a transmission line, the system comprising: 
 an equalizer circuit, comprising: 
 a differential pair defining first and second inputs;  
 a reactive load circuit coupled to the differential pair; and  
 a pair of input follower circuits configured to receive the video data signals and feedback signals from the reactive load and generate corresponding first and second input signals for the first and second inputs of the differential pair; and  
   a control data extension circuit, comprising: 
 a voltage clamp connected to the receive end of the transmission line and operable to clamp a reflection signal caused by the control data signals received at the receive end of the transmission line; and  
 a current booster circuit connected to the receive end of the transmission line and operable to provide a boost current at the receive end of the transmission line when the display control data signal exceeds a first reference value and to eliminate the boost current from the receive end of the transmission line when the control data signal exceeds a second reference value.  
   
     
     
         2 . The system of  claim 1 , wherein the pair of input follower circuits are further configured to provide unity gain.  
     
     
         3 . The system of  claim 2 , wherein the input follower circuits comprise: 
 a first operational amplifier configured to receive as input a first video data signal and to receive a first feedback signal from the reactive load and generate the first input signal applied to the first input; and    a second operational amplifier configured to receive as input a second video data signal and to receive a second feedback signal from the reactive load and generate the second input signal applied to the second input.    
     
     
         4 . The system of  claim 1 , wherein the voltage clamp comprises: 
 a first comparator configured to receive as input the video data signal and a first reference potential and to output a switch signal; and    a first switch configured to receive the switch signal and to couple the receive end of the transmission line to a second reference potential when the video data signal is less than the first reference potential.    
     
     
         5 . The system of  claim 4 , wherein the first and second reference potentials are a ground potential.  
     
     
         6 . The system of  claim 1 , wherein the current booster circuit comprises: 
 a boost current circuit connected to the receive end of the transmission line, the boost current circuit operable to provide the boost current during an activated state; and    a detector circuit operable to monitor the control data signal on the receive end of the transmission line and to activate the boost current circuit when the control data signal exceeds the first reference value and to deactivate the boost current circuit when the control data signal exceeds the second reference value.    
     
     
         7 . The system of  claim 6 , wherein the detector circuit comprises: 
 a level detector operable to output a first data signal when the control data signal is less than the first reference value, and to output a second data signal when the control data signal is greater than the first reference value and less than the second reference value, and to output a third data signal when the control data signal is greater than the second reference value; and    a latch circuit operable to receive the output data signals of the level detector and in response to selectively activate and deactivate the boost current circuit.    
     
     
         8 . The system of  claim 1 , wherein the transmission line is a bus line.  
     
     
         9 . The system of  claim 1 , wherein the transmission line is a cable external to a computer device.  
     
     
         10 . A digital communication system for processing video data signals and control data signals over a transmission line, the system comprising: 
 an equalizer circuit operable to receive video data signals transmitted over the transmission line and output equalized video data signals.    
     
     
         11 . The system of  claim 10 , further comprising: 
 a compensation circuit operable to compensate for intermediate circuitry attenuation of the video data signals.    
     
     
         12 . The system of  claim 10 , further comprising: 
 a control data extension circuit operable to inject a boost current at a receive end of the transmission line during a positive transition in the control data signals.    
     
     
         13 . The system of  claim 10 , wherein the open-loop equalizer circuit comprises: 
 a differential pair defining first and second inputs;    a reactive load circuit coupled to the differential pair; and    a pair of input follower circuits configured to receive the video data signals and feedback signals from the reactive load and generate corresponding first and second input signals for the first and second inputs of the differential pair.    
     
     
         14 . The equalizer circuit of  claim 13 , wherein the pair of input follower circuits are further configured to provide unity gain.  
     
     
         15 . The equalizer circuit of  claim 14 , wherein the input follower circuits comprise: 
 a first operational amplifier configured to receive as input a first video data signal and to receive a first feedback signal from the reactive load and generate the first input signal applied to the first input; and    a second operational amplifier configured to receive as input the second video data signal and to receive a second feedback signal from the reactive load and generate the second input signal applied to the second input.    
     
     
         16 . The equalizer circuit of  claim 14 , wherein the differential pair comprises first and second field effect transistors.  
     
     
         17 . The equalizer circuit of  claim 14 , wherein: 
 the source of the first field effect transistor is connected to an input node of the first operational amplifier to provide the first feedback signal; and    the source of the second field effect transistor is connected to an input node of the second operational amplifier to provide the second feedback signal.    
     
     
         18 . The system of  claim 10 , wherein the open-loop equalizer circuit comprises: 
 a differential pair defining first and second input nodes and first and second output nodes;    a reactive load circuit coupled to the differential pair;    a first input follower circuit connected to the first input node of the differential pair, the first input follower circuit operable to receive a first video data signal and to receive a first feedback signal from the differential pair and in response to generate a first input signal at the first input node of the differential pair; and    a second input follower circuit connected to the second input node of the differential pair, the second input follower circuit operable to receive a second video data signal and to receive a second feedback signal from the differential pair and in response to generate a second input signal at the second input node of the differential pair;    wherein the equalized video data signals are generated at the first and second output nodes, respectively.    
     
     
         19 . The system of  claim 18 , wherein: 
 the first input follower circuit comprises a first operational amplifier configured to receive as input the first video data signal and to receive the first feedback signal and provide unity feedback to generate the first input signal; and    the second input follower circuit comprises a second operational amplifier configured to receive as input the second video data signal and to receive the second feedback signal and provide unity feedback to generate the second input signal.    
     
     
         20 . The system of  claim 19 , wherein the differential pair comprises first and second field effect transistors.  
     
     
         21 . The system of  claim 20 , wherein: 
 the source of the first field effect transistor is connected to an input node of the first operational amplifier to provide the first feedback signal; and    the source of the second field effect transistor is connected to an input node of the second operational amplifier to provide the second feedback signal.    
     
     
         22 . The system of  claim 21 , wherein the reactive load circuit comprises a resistive and capacitive network.  
     
     
         23 . The system of  claim 11 , wherein the compensation circuit operable to compensate for intermediate circuitry comprises an electrostatic discharge (ESD) compensation circuit, the ESD compensation circuit comprising: 
 a differential pair defining first and second inputs and first and second outputs;    a reactive load circuit coupled to the differential pair;    a pair of input follower circuits configured to receive as input the video data signals at the ESD protection circuitry and feedback signals from the reactive load, and to generate corresponding first and second input signals for the first and second inputs of the differential pair, and to further generate compensated video data signals at the first and second outputs to compensate for video data signal attenuation caused by the ESD protection circuitry.    
     
     
         24 . The system of  claim 23 , wherein the reactive load circuit comprises a resistive and capacitive network having a frequency response inversely proportional to the frequency response of the ESD protection circuitry.  
     
     
         25 . The system of  claim 12 , wherein the control data extension circuit comprises: 
 a voltage clamp connected to the receive end of the transmission line and operable to clamp a reflection signal caused by the control data signals received at the receive end of the transmission line; and    a current booster circuit connected to the receive end of the transmission line and operable to provide the boost current at the receive end of the transmission line when the control data signal exceeds a first reference value and to eliminate the boost current from the receive end of the transmission line when the control data signal exceeds a second reference value.    
     
     
         26 . The system of  claim 25 , wherein the voltage clamp comprises: 
 a first comparator configured to receive as input the control data signal and a first reference potential and to output a switch signal; and    a first switch configured to receive the switch signal and to couple the receive end of the transmission line to a second reference potential when the control data signal is less than the first reference potential.    
     
     
         27 . The system of  claim 26 , wherein the first and second reference potentials are a ground potential.  
     
     
         28 . The system of  claim 25 , wherein the current booster circuit comprises: 
 a boost current circuit connected to the receive end of the transmission line, the boost current circuit operable to provide the boost current during an activated state; and    a detector circuit operable to monitor the control data signal on the receive end of the transmission line and to activate the boost current circuit when the control data signal exceeds the first reference value and to deactivate the boost current circuit when the control data signal exceeds the second reference value.    
     
     
         29 . The system of  claim 28 , wherein the detector circuit comprises: 
 a level detector operable to output a first data signal when the control data signal is less than the first reference value, and to output a second data signal when the control data signal is greater than the first reference value and less than the second reference value, and to output a third data signal when the control data signal is greater than the second reference value; and    a latch circuit operable to receive the output data signals of the level detector and in response to selectively activate and deactivate the boost current circuit.    
     
     
         30 . The system of  claim 29 , wherein: 
 the first reference value is a first reference voltage greater than a logic 0 voltage signal; and    the second reference value is a second reference voltage greater than the first reference voltage.    
     
     
         31 . The system of  claim 28 , wherein the detector circuit comprises: 
 a first comparator configured to receive as input the control data signal and the first reference value and output a first comparator signal;    a second comparator configured to receive as input the control data signal and the second reference value and output a second comparator signal; and    a latch configured to receive as input the first and second comparator signals and output a latch signal.    
     
     
         32 . The system of  claim 12 , wherein the control data extension circuit comprises: 
 a current booster circuit connected to the receive end of the transmission line, the current booster circuit operable to inject a boost current at the receive end of the transmission line during a positive transition in the control data signal, and to eliminate the boost current at the end of the positive transition in the control data signal and prevent injection of the boost current at the receive end of the transmission line during a negative transition in the control data signal.    
     
     
         33 . The circuit of  claim 32 , wherein the current booster circuit is adapted to inject the boost current at the receive end of the transmission line when the control data signal exceeds a first reference value and eliminate the boost current from the receive end of the transmission line when the control data signal exceeds a second reference value, and to prevent injection of the boost current at the receive end of the transmission line when the control data signal falls below the second and first reference values.  
     
     
         34 . The system of  claim 11 , further comprising: 
 a control data extension circuit operable to inject a boost current at a receive end of the transmission line during a positive transition in the control data signals.    
     
     
         35 . The system of  claim 10 , wherein the open-loop equalizer is connected to a transmit end of the transmission line.  
     
     
         36 . The system of  claim 10 , wherein the open-loop equalizer is connected to the receive end of the transmission line.  
     
     
         37 . The system of  claim 10 , wherein the transmission line is a bus line.  
     
     
         38 . The system of  claim 10 , wherein the transmission line is a cable external to a computer device.  
     
     
         39 . The system of  claim 12 , wherein the control data extension circuit is coupled to a bi-directional communication line in the transmission line.