Wafer level semiconductor module and method for manufacturing the same

Abstract

A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.

1 . A wafer level semiconductor module comprising:
 a module board; and   an IC chip set mounted on the module board, the IC chip set including:
 a plurality of IC chips having scribe line areas between adjacent IC chips, 
 each IC chip having a semiconductor substrate with an active surface with a plurality of chip pads and a back surface, 
 a passivation layer provided on the active surface of the semiconductor substrate of each IC chip having openings through which the chip pads are exposed, and 
 sealing portions provided in the scribe line areas. 
   
   
   
       2 . The module of  claim 1 , wherein the sealing portions have a width substantially equal to a width of the corresponding scribe line areas. 
   
   
       3 . The module of  claim 1 , wherein each IC chip has an interlayer dielectric layer provided on the active surface of the semiconductor substrate, a redistribution layer provided on the interlayer dielectric layer, and an insulating layer provided on the redistribution layer. 
   
   
       4 . The module of  claim 3 , wherein the sealing portions are integral with the interlayer dielectric layer. 
   
   
       5 . The module of  claim 3 , wherein the sealing portions are integral with the insulating layer. 
   
   
       6 . The module of  claim 1 , wherein the sealing portions are formed in a multilayered structure. 
   
   
       7 . The module of  claim 1 , wherein the sealing portions are formed from polymer composition. 
   
   
       8 . The module of  claim 7 , wherein the polymer composition includes lower-temperature-cured polymer. 
   
   
       9 . The module of  claim 1 , wherein the sealing portions are formed from at least one elastomer composition. 
   
   
       10 . The module of  claim 3 , further comprising external connection terminals provided on the redistribution layer and configured to connect the IC chip set to the module board. 
   
   
       11 . The module of  claim 10 , wherein the external connection terminals are arranged at uniform intervals. 
   
   
       12 . The module of  claim 1 , wherein the back surface of each IC chip has a protection layer. 
   
   
       13 . The module of  claim 12 , wherein the protection layer is an adhesive tape. 
   
   
       14 . The module of  claim 1 , wherein the plurality of IC chips provided are in a matrix arrangement. 
   
   
       15 . A method for manufacturing a wafer level semiconductor module comprising:
 providing a wafer having an IC chip set having a plurality of IC chips and scribe line areas between adjacent IC chips, each IC chip having a semiconductor substrate having an active surface with a plurality of chip pads and a back surface;   forming trenches in the scribe line areas; and.   filling the trenches to form sealing portions.   
   
   
       16 . The method of  claim 15 , further comprising:
 separating the wafer into IC chip sets; and   mounting the IC chip set on the module board.   
   
   
       17 . The method of  claim 15 , wherein the trenches have a width substantially equal to a width of the corresponding scribe line areas. 
   
   
       18 . The method of  claim 15 , further comprising:
 forming a passivation layer on the active surface of the semiconductor substrate exposing the chip pads;   forming an interlayer dielectric layer on the passivation layer;   forming a redistribution layer connected to the chip pads on the passivation layer;   forming an insulating layer on the redistribution layer and the interlayer dielectric layer to expose a portion of the redistribution layer.   
   
   
       19 . The method of  claim 18 , wherein the sealing portions are formed integrally with the interlayer dielectric layer. 
   
   
       20 . The method of  claim 18 , wherein the sealing portions are formed integrally with the insulating layer. 
   
   
       21 . The method of  claim 15 , wherein the sealing portions are formed in a multilayered structure. 
   
   
       22 . The method of  claim 16 , wherein the wafer is separated into IC chips sets having a matrix arrangement. 
   
   
       23 . The method of  claim 15 , wherein the sealing portions are formed by providing polymer in the trenches. 
   
   
       24 . The method of  claim 23 , wherein the polymer is a lower-temperature-cured polymer. 
   
   
       25 . The method of  claim 15 , wherein the sealing portions are formed by providing elastomer in the trenches. 
   
   
       26 . The method of  claim 18 , wherein the redistribution layer is a multilayered redistribution layer formed using the interlayer dielectric layer. 
   
   
       27 . The method of  claim 18 , further comprising removing a portion of the back surface of the semiconductor substrate to expose a portion of the sealing portion. 
   
   
       28 . The method of  claim 27 , further comprising:
 forming a protection layer on the wafer where the back surface was removed.   
   
   
       29 . The method of  claim 28 , wherein the protection layer is an adhesive tape. 
   
   
       30 . The method of  claim 18 , further comprising:
 providing external connection terminals on the exposed portion of the redistribution layer.   
   
   
       31 . The method of  claim 30 , wherein the external connection terminals are arranged over the IC chip set at uniform intervals.