Structure and fabrication of self-aligned high-performance organic fets

Abstract

A low channel length organic field-effect transistor can be produced in high volume and at low cost. The transistor structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor layer, a second dielectric layer, and a third conductor layer acting as the gate terminal. In this structure, the transistor is formed on the edge of the first dielectric between the first conductor layer and the second conductor layer. The second conductor layer is deposited on the raised surfaces formed by the dielectric such that conductive ink does not flow into the trough between the dielectric raised surfaces. This is accomplished by coating a flat or rotary print plate with the conductive ink, and applying the appropriate pressure to deposit the materials only on the raised surfaces of the dielectric. The second metal is automatically aligned to the layer beneath it. Due to this self-alignment and the short channel formed by the thickness of the dielectric material, a high-performance FET is produced without the requirement of high-resolution lithography equipment.

We claim:  
     
         1 . An organic field-effect transistor comprising: 
 a patterned dielectric layer having a raised surface;    a source or drain conductor layer; and    a vertical transistor structure, wherein the source or drain conductor layer is deposited as a self-aligned layer to the underlying dielectric layer by applying the conductor layer only to the raised surface of the dielectric layer.    
     
     
         2 . An organic field-effect transistor comprising: 
 a substrate layer;    a metal source layer formed on the substrate layer;    a first dielectric layer formed on the substrate layer having a sloped edge, the sloped edge forming the channel length of the transistor;    a self-aligned metal drain layer formed on the first dielectric layer;    a semiconductor layer formed on the sloped edge of the first dielectric layer; and    a metal gate layer formed on the semiconductor layer.    
     
     
         3 . The organic field-effect transistor of  claim 1  further comprising openings in the semiconductor and second dielectric layers to allow contact to the metal source layer.  
     
     
         4 . The organic field-effect transistor of  claim 1  further comprising openings in the semiconductor and second dielectric layers to allow contact to the metal drain layer.  
     
     
         5 . A method of fabricating an organic field-effect transistor comprising: 
 forming a substrate layer;    forming a metal source layer on the substrate layer;    forming a first dielectric layer on the substrate layer having a sloped edge, the sloped edge forming the channel length of the transistor;    forming a self-aligned metal drain layer on the first dielectric layer;    forming a semiconductor layer formed on the sloped edge of the first dielectric layer; and    forming a metal gate layer formed on the semiconductor layer.    
     
     
         6 . The method of  claim 5  further comprising forming openings in the semiconductor and second dielectric layers to allow contact to the metal source layer.  
     
     
         7 . The method of  claim 5  further comprising forming openings in the semiconductor and second dielectric layers to allow contact to the metal drain layer.  
     
     
         8 . The method of  claim 5 , wherein forming the self-aligned metal drain layer comprises: 
 coating the surface of a print plate with ink comprising a solution-based conductor; and    applying the print plate to transfer the ink to a raised surface of the first dielectric layer, but not transferring the ink to troughs in the first dielectric layer.    
     
     
         9 . The method of  claim 8 , wherein the pressure of the print plate is adjusted to optimize ink transfer only to a raised surface of the first dielectric layer, the optimized pressure being evidenced by a substantial lack of ink in the troughs in the first dielectric layer.  
     
     
         10 . The method of  claim 8 , wherein the material of the print plate is chosen to optimize ink transfer only to a raised surface of the dielectric, the optimized plate material being evidenced by a substantial lack of ink in the troughs in the first dielectric layer.  
     
     
         11 . The method of  claim 8 , wherein the slope of first dielectric layer edge is controlled by adjusting the surface tension of the ink used to form the first dielectric layer and the surface energy of the metal source layer.  
     
     
         12 . The method of  claim 11 , wherein the surface tension of the ink used to form the first dielectric layer is modified by adding surfactants or by adjusting the weight-to-solid ratio of the ink solution.  
     
     
         13 . The method of  claim 1  wherein the surface energy of the metal source layer is adjusted through corona treatment, oxygen plasma treatment, ultra-violet exposure, ozone treatments, or application of a material designed to modify the surface energy.  
     
     
         14 . The method of  claim 5  further comprising forming a first organic field-effect transistor, a second organic field-effect transistor, and a metal gate layer common to the first and second organic field-effect transistors.  
     
     
         15 . The method of  claim 5 , wherein the metal source layer is formed using a solution-based conductor, including flake silver ink, flake gold ink, nano-particle silver ink, nano-particle gold ink, PEDOT, polythiophene, and polyanalene.  
     
     
         16 . The method of  claim 8 , wherein the print plate is coated with a conductive ink comprising a solution-based flake conductor ink, solution-based nano-particle metal ink, PEDOT, polyanalyene, polythiophene, or other solution-based conductive fluid.  
     
     
         17 . The method of  claim 5 , wherein the semiconductor layer is formed using low molecular materials comprising pentacene, hexithiphene, TPD, and PBD.  
     
     
         18 . The method of  claim 5 , wherein the semiconductor layer is formed using polymer materials comprising polythiophene, parathenylene vinylene, and polyphenylene ethylene.  
     
     
         19 . The method of  claim 5 , wherein the semiconductor layer is formed using hybrid materials comprising polyvinyl carbazole.  
     
     
         20 . The method of  claim 5 , wherein the second dielectric layer is formed using a printable material comprising spin-on-glass or a polymer-based dielectric comprising cross-linked polyvinylphenol (PVP), polypropylene, CYTOP, polyvinylalcohol, polyisobutylene, PMMA, polyethylene terephthalate (PET), poly-p-xylylene, and CYMM.