Method and system for a user space TCP offload engine (TOE)

Abstract

Certain aspects of a method and system for user space TCP offload are disclosed. Aspects of a method may include offloading transmission control protocol (TCP) processing of received data to an on-chip processor. The received data may be posted directly to hardware, bypassing kernel processing of the received data, utilizing a user space library. If the received data is not cached in memory, an application buffer comprising the received data may be registered by the user space library. The application buffer may be pinned and posted to the hardware.

1 . A method for handling processing of network information, the method comprising:
 offloading transmission control protocol (TCP) processing of received data to an on-chip processor; and   posting said received data directly to hardware, bypassing kernel processing of said received data, utilizing a user space library.   
   
   
       2 . The method according to  claim 1 , further comprising determining if said received data is cached in memory. 
   
   
       3 . The method according to  claim 2 , further comprising registering at least one application buffer comprising said received data if said received data is not cached in said memory. 
   
   
       4 . The method according to  claim 3 , further comprising pinning said at least one application buffer comprising said received data if said received data is not cached in said memory. 
   
   
       5 . The method according to  claim 4 , further comprising posting said pinned said at least one application buffer comprising said received data to said hardware if said received data is not cached in said memory. 
   
   
       6 . The method according to  claim 3 , further comprising:
 adding an application buffer virtual address to a buffer ID of said at least one application buffer; and   storing said at least one application buffer in cache memory.   
   
   
       7 . The method according to  claim 2 , further comprising posting said received data directly to said hardware bypassing kernel processing of said received data if said received data is cached in said memory. 
   
   
       8 . The method according to  claim 1 , further comprising pre-posting at least one application buffer comprising said received data to said hardware. 
   
   
       9 . The method according to  claim 1 , further comprising indicating receipt of said data by updating a completion queue entry in said hardware. 
   
   
       10 . The method according to  claim 9 , further comprising generating an event notification after updating said completion queue entry in said hardware. 
   
   
       11 . A system for handling processing of network information, the system comprising:
 circuitry that enables offloading transmission control protocol (TCP) processing of received data to an on-chip processor; and   circuitry that enables posting of said received data directly to hardware, bypassing kernel processing of said received data, utilizing a user space library.   
   
   
       12 . The system according to  claim 11 , further comprising circuitry that enables determining if said received data is cached in memory. 
   
   
       13 . The system according to  claim 12 , further comprising circuitry that enables registration of at least one application buffer comprising said received data if said received data is not cached in said memory. 
   
   
       14 . The system according to  claim 13 , further comprising circuitry that enables pinning of said at least one application buffer comprising said received data if said received data is not cached in said memory. 
   
   
       15 . The system according to  claim 14 , further comprising circuitry that enables posting of said pinned said at least one application buffer comprising said received data to said hardware if said received data is not cached in said memory. 
   
   
       16 . The system according to  claim 13 , further comprising:
 circuitry that enables adding of an application buffer virtual address to a buffer ID of said at least one application buffer; and   circuitry that enables storage of said at least one application buffer in cache memory.   
   
   
       17 . The system according to  claim 12 , further comprising circuitry that enables posting of said received data directly to said hardware bypassing kernel processing of said received data if said received data is cached in said memory. 
   
   
       18 . The system according to  claim 11 , further comprising circuitry that enables pre-posting of at least one application buffer comprising said received data to said hardware. 
   
   
       19 . The system according to  claim 11 , further comprising circuitry that enables indication of receipt of said data by updating a completion queue entry in said hardware. 
   
   
       20 . The system according to  claim 19 , further comprising circuitry that enables generation of an event notification after updating said completion queue entry in said hardware.