Voltage regulator with suspend mode

Abstract

A system is disclosed. The system includes a central processing unit (CPU) to operate in one or more low power sleep states, and a power converter. The power converter includes phase inductors; and one or more power switches to drive the phase inductors. The one or more power switches are deactivated during the CPU sleep state.

1 . A system comprising: 
 a central processing unit (CPU) to operate in one or more low power sleep states; and    a power converter having: 
 phase inductors; and  
 one or more power switches to drive the phase inductors, wherein  
   the one or more power switches are deactivated during the CPU sleep state.    
   
   
       2 . The system of  claim 1  wherein the CPU comprises a power control unit to regulate the output voltage from the power converter and to suspend operation of the power converter whenever the CPU enters into the sleep state.  
   
   
       3 . The system of  claim 2  wherein a clock that supplies the power control unit is deactivated in the CPU sleep state.  
   
   
       4 . The system of  claim 2  wherein the one or more power switches are field effect transistors (FETs);  
   
   
       5 . The system of  claim 4  wherein the power converter further comprises: 
 a set of phases, wherein each phase includes: 
 a phase inductor having an upper FET coupling a primary power supply voltage to a first terminal of the phase inductor, and  
 a lower FET coupling ground to the first terminal of the phase inductor; and  
   output filter capacitors.    
   
   
       6 . The system of  claim 5  wherein charge stored at the output capacitors supply power to the CPU whenever the operation of the power converter is suspended.  
   
   
       7 . The system of  claim 6  wherein the power control unit activates the power switches once the CPU exits the sleep state.  
   
   
       8 . The system of  claim 6  wherein the power control unit monitors the voltage level at the CPU whenever the operation of the power converter is suspended.  
   
   
       9 . The system of  claim 8  wherein the power control unit activates the power FETs upon detecting that the voltage at the CPU has fallen below a predetermined threshold voltage.  
   
   
       10 . The system of  claim 9  wherein the power control unit suspends operation of the power converter after the voltage has risen to the predetermined threshold voltage.  
   
   
       11 . The system of  claim 8  wherein whenever the CPU is in the sleep state and the CPU voltage is above a threshold voltage the power converter will enter an adaptive diode emulation mode.  
   
   
       12 . A method comprising: 
 determining whether a central processing unit (CPU) has entered a sleep state; and    a power control unit suspending operation of power switches within a power converter if the CPU has entered into the sleep state.    
   
   
       13 . The method of  claim 12  wherein suspending the operation of the power converter further comprises supplying power to the CPU via charge stored at output capacitors within the power converter.  
   
   
       14 . The method of  claim 12  further comprising the power control unit activating the power switches once the CPU exits the sleep state.  
   
   
       15 . The method of  claim 12  further comprising the power control unit monitoring the voltage level at the CPU whenever the operation of the power converter has been suspended.  
   
   
       16 . The method of  claim 15  further comprising the power control unit activating the FETs upon detecting that the voltage at the CPU has fallen below a predetermined threshold voltage.  
   
   
       17 . The method of  claim 15  further comprising the power converter entering an adaptive diode emulation mode whenever the CPU is in the sleep state and the CPU voltage is above a threshold voltage.  
   
   
       18 . A power converter comprising: 
 phase inductors; and    one or more power switches to drive the phase inductors, wherein the one or more power switches are deactivated upon receiving a signal indicating that a central processing unit (CPU) has entered a sleep state.    
   
   
       19 . The power converter of  claim 18  wherein the one or more power switches are field effect transistors (FETs).  
   
   
       20 . The power converter of  claim 19  wherein the power converter further comprises: 
 a set of phases, wherein each phase includes: 
 a phase inductor having an upper FET coupling a primary power supply voltage to a first terminal of the phase inductor, and  
 a lower FET coupling ground to the first terminal of the phase inductor; and  
   output filter capacitors.    
   
   
       21 . The power converter of  claim 20  wherein charge stored at the output capacitors supply power to the CPU whenever the operation of the power converter is suspended.  
   
   
       22 . The power converter of  claim 18  wherein whenever the CPU is in the sleep state and the CPU voltage is above a threshold voltage the power converter will enter an adaptive diode emulation mode.