Semiconductor substrate-based interconnection assembly for semiconductor device bearing external elements

Abstract

The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls on a die, partial wafer or wafer under test for testing and burn-in. The interconnections are formed in recesses sized and shaped to receive and contain approximately 10% to 50%, and preferably about 30%, of the total height of each solder ball within its associated interconnection. Such a design compensates for under-sized or misshapen solder balls on the die under test and thereby prevents a possible false failure indication for the die under test. This design also distributes the forces on the solder ball caused by biasing the die under test to its temporary package to the periphery of the solder ball and thus reduces the likelihood of damage to the solder ball or the semiconductor substrate.

1 - 12 . (canceled)  
     
     
         13 . A method of fabricating an interconnection structure on a substrate, the method comprising: 
 etching a via to a selected size and shape in a passivation layer disposed on a substrate;    forming a conductive trace in communication with the via; and    forming at least one metal layer over a portion of the conductive trace within the via, over walls thereof and over a periphery of the surface of the passivation layer proximate the via to form an interconnection structure configured for receiving a portion of a substantially spherical interconnection element projecting from a surface of a semiconductor device to a height, wherein the interconnection structure is dimensioned to receive the portion of the substantially spherical interconnection element to an extent of approximately 10% to 50% of the height thereof.    
     
     
         14 . The method of  claim 13 , wherein the interconnection structure is dimensioned to receive the portion of the substantially spherical interconnection element to an extent of approximately 30% of the height thereof.  
     
     
         15 . The method of  claim 13 , wherein etching the via comprises facet etching to form a via having sloped walls.  
     
     
         16 . The method of  claim 13 , wherein etching the via comprises successive masking and etching steps to form a via having stepped walls.  
     
     
         17 . The method of  claim 13 , further comprising forming a dielectric layer over the substrate, forming the passivation layer over the dielectric layer, and wherein etching the via in the passivation layer comprises etching the via through the passivation layer to proximate the dielectric layer.  
     
     
         18 . The method of  claim 18 , further comprising forming the conductive trace over the dielectric layer prior to etching the via, and exposing a portion of the conductive trace by the etching.  
     
     
         19 . The method of  claim 13 , further comprising forming the conductive trace over the passivation layer and into the via after etching thereof.  
     
     
         20 . An article for contacting at least one interconnection element of at least one semiconductor device, the article comprising: 
 a substrate having a passivation layer thereon;    at least one conductive trace; and    a metal-lined via comprising at least one layer of metal extending through the passivation layer and in electrical communication with the at least one conductive trace, wherein the metal-lined via is sized and configured to receive, without deformation, a substantially spherical interconnection element protruding to a height from at least one semiconductor device to a depth corresponding to approximately 10% to 50% of the height of the substantially spherical interconnection element and establish an electrical connection therewith at the depth by way of biased contact of only a portion of an interior surface of the metal-lined via with only a portion of an exterior surface of the substantially spherical interconnection element received therewithin.    
     
     
         21 . The article of  claim 20 , wherein the metal-lined is configured of a size and shape to receive approximately 30% of the height of the substantially spherical interconnection element.  
     
     
         22 . The article of  claim 20 , wherein the metal-lined via includes sloped sidewalls.  
     
     
         23 . The article of  claim 20 , wherein the metal-lined via includes stepped sidewalls.  
     
     
         24 . The article of  claim 20 , wherein the at least one conductive trace comprises copper.  
     
     
         25 . The article of  claim 20 , wherein the passivation layer comprises polyimide.  
     
     
         26 . The article of  claim 20 , wherein the metal-lined via comprises a metal from the group comprising gold, platinum, palladium, and tungsten.  
     
     
         27 . The article of  claim 20 , wherein the passivation layer has a thickness of about 100 microns or less.  
     
     
         28 . The article of  claim 20 , wherein the passivation layer has a thickness of about 20 to 25 microns.  
     
     
         29 . The article of  claim 20 , wherein the at least one conductive trace extends over the passivation layer and into the via under the at least one layer of metal.  
     
     
         30 . The article of  claim 20 , wherein the at least one conductive trace lies on a dielectric layer between the passivation layer and the substrate, and a portion thereof at a bottom of the via is in contact with the at least one layer of metal.  
     
     
         31 . The substrate of  claim 30 , wherein the dielectric layer comprises silicon dioxide.  
     
     
         32 . The article of  claim 20 , wherein the metal-lined via is sized and configured to establish the electrical connection only along at least one contact line consisting of the portion of the interior surface of the metal-lined via at least partially circling the portion of the exterior surface of the substantially spherical interconnection element.