Method and apparatus for forming a semiconductor substrate with a layer structure of activated dopants

Abstract

Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant at a first doping concentration. Then a solid phase epitaxy regrowth step is performed on a thin layer of desired thickness of the amorphized region, in order to activate the first dopant only in this thin layer. Subsequently, a second dopant is implanted in the remaining amorphous region at a second doping concentration. Subsequent annealing of the substrate activates the second dopant only in said remaining region, so a very abrupt transition between dopant characteristics of the thin layer with first dopant and the region with the second dopant is obtained.

1 . A transistor for an integrated circuit device, comprising: 
 a gate insulating layer formed on a semiconductor substrate;    a gate conductor formed on the gate insulator layer;    a first transistor electrode and a second transistor electrode;    a first and second transistor electrode extension having a first dopant connected, respectively, to each of the first transistor electrode and the second transistor electrode, wherein the first and second transistor electrode extensions abut the gate insulating layer; and    a first and second boundary region having a second dopant configured, respectively, at least partially surrounding each transistor electrode extension, wherein each boundary region has a concentration abruptness of at least 1 nm/decade.    
   
   
       2 . The transistor of  claim 1 , wherein the boundary layer has a thickness of between about 0.5 nm and 5 nm.  
   
   
       3 . The transistor of  claim 2 , wherein the boundary layer has a thickness of between about 1 nm and 3 nm.  
   
   
       4 . The transistor of  claim 1 , wherein the gate conductor comprises a metal.  
   
   
       5 . The transistor of  claim 1 , wherein the gate insulating layer comprises a thermal oxide layer.