Semiconductor wafer and method for making the same

Abstract

A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the dicing line. Each of the WAT pads has thereon a slot opening. A reinforcement structure is formed within the slot opening and penetrates through the WAT pad for stopping propagation of de-lamination during wafer dicing.

1 . A method of dicing a semiconductor wafer, comprising: 
 forcing a plurality of active circuit die areas on a semiconductor wafer, each of the active circuit die areas being bordered by a dicing line;    forming a plurality of pads in the dicing line;    forming a reinforcing structure in the pads and along at least one side of each said pad; and    dicing the semiconductor wafer along the dicing line.    
   
   
       2 . The method according to  claim 1  wherein the reinforcing structure comprises a plurality of vias in a plurality of dielectric layers.  
   
   
       3 . The method according to  claim 2  wherein the plurality of vias comprises at least one row of vias.  
   
   
       4 . The method according to  claim 2  wherein the plurality of vias comprises at least a via bar.  
   
   
       5 . The method according to  claim 2  wherein the plurality of vias have air gap therein.  
   
   
       6 . The method according to  claim 2  wherein the plurality of vias are filled with metal.  
   
   
       7 . The method according to  claim 6  wherein the metal comprises copper.  
   
   
       8 . The method according to  claim 1  wherein the reinforcing structure is disposed along two sides of each said pad in parallel with the dicing line.