Computer processor architecture selectively using finite-state-machine for control code execution

Abstract

A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available. A microinstruction is identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.

1 - 8 . (canceled)  
   
   
       9 . A computer processor for executing a microinstruction, the computer processor comprising: 
 a configurable finite state machine (FSM);    processing circuitry; and    control circuitry for controlling the configurable finite state machine (FSM) to implement at least a portion of the microinstruction in parallel with the processing circuitry.    
   
   
       10 . The computer processor of  claim 9 , wherein the configurable finite state machine (FSM) and processing circuitry are operated concurrently.  
   
   
       11 . (canceled)  
   
   
       12 . A method of performing an operation according to a microinstruction having a finite state machine control field, comprising: 
 storing data associated with the operation to be performed;    configuring a configurable finite state machine via a finite state machine configuration circuit to perform a function in association with the operation;    detecting a predefined value in the finite state machine control field in the microinstruction; and    providing data to enable execution of the function by the finite state machine in response to the predefined value.    
   
   
       13 . The method of  claim 12 , further comprising configuring a second configurable finite state machine via the finite state configuration circuit to perform a second function in association with the operation.  
   
   
       14 . The method of  claim 12 , further comprising configuring the configurable finite state machine in advance to perform the function associated with the microinstruction.  
   
   
       15 . The method of  claim 12 , wherein a second microinstruction having the same function as the first microinstruction is executed by the finite state machine.  
   
   
       16 . A method of processing a microinstruction using a plurality of finite state machines in a processing system, the microinstruction including a finite state machine data field and directing at least one operation, the method comprising: 
 reading the microinstruction;    determining the at least one operation directed by the microinstruction to be performed;    selecting one of the plurality of finite state machines to perform the at least one operation of the microinstruction; and    configuring the selected finite state machine to perform the at least one operation of the microinstruction.    
   
   
       17 . The method of  claim 16 , wherein the finite state machine is selected by hardware within the processing system.  
   
   
       18 . The method of  claim 16 , wherein the finite state machine is selected by a source external to the processing system.  
   
   
       19 . The method of  claim 16 , wherein the configuration of the selected finite state machine occurs prior to reading the microinstruction.  
   
   
       20 . The method of  claim 16 , wherein the microinstruction includes configuration data used to select the finite state machine and control data to control the performance of the operation via the finite state machine.  
   
   
       21 . The method of  claim 16 , wherein the finite state machine is selected from the plurality of finite state machines based on the use of the plurality of finite state machines in the processing system.  
   
   
       22 . The method of  claim 16 , wherein the finite state machine is selected based on power requirements.  
   
   
       23 . The method of  claim 16 , wherein configuring the finite state machine is performed via a hardwired configuration circuit.  
   
   
       24 . The method of  claim 16 , wherein configuring the finite state machine is performed via the microinstruction.  
   
   
       25 . A method for executing software with a computer processor having a configurable finite state machine, control circuitry for configuring the configurable finite state machine to perform different operations, and processing circuitry, the method comprising: 
 reading the software;    deriving at least one microinstruction from the software, the microinstruction including directing an operation;    determining whether the operation should be executed using the configurable finite state machine;    providing an instruction that the operation is to be executed by the configurable finite state machine based on the determination; and    executing the operation with the configurable finite state machine.    
   
   
       26 . A processor system for processing a microinstruction including a finite state machine data field and directing at least one operation, the processor comprising: 
 a plurality of finite state machines;    an input device to read the microinstruction;    a controller to determine the at least one operation directed by the microinstruction to be performed and to select one of the plurality of finite state machines to perform the at least one operation of the microinstruction; and    a configuration circuit to configure the selected finite state machine to perform the at least one operation of the microinstruction.    
   
   
       27 . The processor system of  claim 26 , wherein controller is hardware within the processing system.  
   
   
       28 . The processor system of  claim 26 , wherein the controller configures the selected finite state machine prior to the input device reading the microinstruction.  
   
   
       29 . The processor system of  claim 26 , wherein the microinstruction includes configuration data used to select the finite state machine and control data to control the performance of the operation via the finite state machine.  
   
   
       30 . The processor system of  claim 26 , wherein the controller selects the finite state machine from the plurality of finite state machines based on the use of the plurality of finite state machines in the processor system.  
   
   
       31 . The processor system of  claim 26 , wherein the controller selects the finite state machine based on power requirements of the processor system.  
   
   
       32 . The processor system of  claim 26 , wherein the configuration circuit is hardwired.  
   
   
       33 . The processor system of  claim 26 , wherein the configuration circuit performs the configuration via reading the microinstruction.