Semiconductor device with leakage current compensating circuit

Abstract

A semiconductor device includes a current mirror circuit having a plurality of transistors; a current source configured to supply a constant reference current to the current mirror circuit through a node; and a compensating circuit configured to supply a compensation current to the node to compensate for at least a part of gate leakage currents of the plurality of transistors. The compensating circuit may supply the compensation current equal to a summation of the gate leakage currents.

1 . A semiconductor device comprising: 
 a current mirror circuit comprising a plurality of transistors;    a current source configured to supply a constant reference current to said current mirror circuit through a node; and    a compensating circuit configured to supply a compensation current to said node to compensate for at least a part of gate leakage currents of said plurality of transistors,    wherein said compensating circuit further comprises:    an activation control circuit configured to allow said current mirror circuit to operate normally in response to a first signal of a first voltage level, and to inhibit said current mirror circuit to operate in response to a second signal of a second voltage level different from said first voltage level.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein said activation control circuit comprises: 
 an inverter supplied with a control signal;    a first transistor arranged between said node and gates of said plurality of transistors other than a specific transistor in said current mirror circuit, wherein said specific transistor has a drain connected with said node, a gate connected with said drain of said specific transistor and the gates of said plurality of transistor other than said specific transistor and a source connected with a ground; and    a control transistor having a gate connected with an output terminal of said inverter, and a drain connected with the gates of said plurality of transistors and a source connected with the ground.    
   
   
       3 . The semiconductor device according to  claim 2 , wherein said inverter outputs a permit signal in response to the first signal to allow said current mirror circuit to operate normally, and outputs an inhibit signal in response to the second signal to inhibit said current mirror circuit to operate.  
   
   
       4 . A method of suppressing gate leakage currents, comprising: 
 supplying a constant reference current from a current source to a current mirror circuit of a plurality of transistors through a node;    supplying a compensation current from a compensating circuit to said current mirror circuit through said node to compensate for at least a part of gate leakage currents of said plurality of transistors;    allowing said current mirror circuit to operate normally in response to a first signal of a first voltage level; and    inhibiting said current mirror circuit to operate in response to a second signal of a second voltage level different from said first voltage level.