Snoop filter directory mechanism in coherency shared memory system

Abstract

Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.

1 . A method of maintaining coherency of data accessed by a remote device, comprising: 
 maintaining, on the remote device, a remote cache directory indicative of memory locations residing in a cache on a processor which shares access to some portion of a memory device;    maintaining, on the remote device, a castout buffer indicating cache lines that have been or will be castout from the processor cache; and    routing memory requests issued at the remote device to the memory device or the processor cache, depending on information contained in the remote cache directory and castout buffer.    
     
     
         2 . The method of  claim 1 , wherein maintaining the remote cache directory comprises: 
 receiving, by the remote device, a bus transaction initiated by the processor containing cache coherency information indicating a change to a cache directory residing on the processor; and    updating the remote cache directory, based on the cache coherency information, to reflect the change to the cache directory residing on the processor.    
     
     
         3 . The method of  claim 2 , wherein maintaining, on the remote device, a buffer indicating cache lines that have been castout from the processor cache comprises copying an entry from the remote cache directory to the castout buffer if the cache coherency information indicates an aging castout is to occur at the processor.  
     
     
         4 . The method of  claim 2 , wherein the cache coherency information comprises a set of bits indicating a way within an associative set.  
     
     
         5 . The method of  claim 1 , wherein routing memory requests issued at the remote device to the memory device or the processor cache, depending on information contained in the remote cache directory and castout buffer comprises: 
 routing memory requests issued at the remote device to memory if an address targeted by the memory request does not match entries in either the remote cache directory or castout buffer.    
     
     
         6 . The method of  claim 5 , further comprising waiting for a castout to occur if an address targeted by the memory request matches an entry in the castout buffer.  
     
     
         7 . The method of  claim 5 , wherein routing memory requests issued at the remote device to the memory device or the processor cache, depending on information contained in the remote cache directory and castout buffer comprises: 
 routing memory requests issued at the remote device to the processor cache if an address targeted by the memory request matches an entry in the remote cache directory.    
     
     
         8 . The method of  claim 7 , further comprising creating an entry in an outstanding transaction buffer containing an address targeted by the memory request routed to the processor cache.  
     
     
         9 . The method of  claim 8 , further comprising removing the entry from the outstanding transaction buffer after receiving response data from the processor.  
     
     
         10 . A method of maintaining coherency of data accessed by a remote device, comprising: 
 maintaining, on the remote device, a remote cache directory indicative of memory locations residing in a cache on a processor which shares access to some portion of a memory device wherein maintaining the remote cache directory comprises: 
 receiving, by the remote device, a bus transaction initiated by the processor containing cache coherency information indicating a change to a cache directory residing on the processor; and  
 updating the remote cache directory, based on the cache coherency information, to reflect the change to the cache directory residing on the processor;  
   routing a memory request issued at the remote device to the processor cache if an address targeted by the memory request matches an entry in the remote cache directory; and    creating an entry in an outstanding transaction buffer residing on the remote device, the entry containing the address targeted by the memory request routed to the processor cache.    
     
     
         11 . The method of  claim 10 , wherein: 
 maintaining, on the remote device, a buffer indicating cache lines that have been castout from the processor cache comprises copying an entry from the remote cache directory to the castout buffer if the cache coherency information indicates an aging castout is to occur at the processor; and    copying an entry from the outstanding transaction buffer to the castout buffer in response to detecting a match between an address of a cache line being castout and the entry.    
     
     
         12 . A device configured to access data stored in memory and cacheable by a processor, comprising: 
 one or more processing cores;    a remote cache directory indicative of contents of a cache residing on the processor;    a castout buffer indicating cache lines that have been or will be castout from the processor cache; and    coherency logic configured to receive cache coherency information indicative of changes to the contents of the processor cache sent by the processor in bus transactions and update the cache directory and castout buffer based on the cache coherency information.    
     
     
         13 . The device of  claim 12 , wherein the coherency logic is configured to: 
 receive cache coherency information indicating a cache line that has been de-allocated by the processor; and    in response, invalidate a corresponding entry in at least one of the remote cache directory and the castout buffer.    
     
     
         14 . The device of  claim 12 , wherein the coherency logic is further configured to: 
 receive, from the processing core, a request to access data associated with a memory location;    examine the remote cache directory for an entry matching an address targeted by the request with a valid coherency state;    examine the castout buffer for an entry matching the address targeted by the request with a valid coherency state; and    if an entry matching the address targeted by the request is not found in either the remote cache directory or castout buffer, route the request to a memory controller to access the requested data from memory without sending a request to the processor.    
     
     
         15 . The device of  claim 14 , wherein: 
 the device further comprises a pending transaction buffer; and    the coherency logic is further configured to route a request to the processor if an entry matching the address targeted by the request is found in the remote cache directory and create an entry in the pending transaction buffer containing the address targeted by the request.    
     
     
         16 . The device of  claim 15 , wherein the memory controller resides on the remote device.  
     
     
         17 . A coherent system, comprising: 
 a processor having a cache for storing data accessed from external memory, a cache directory with entries indicating which memory locations are stored in cache lines of the cache and corresponding coherency states thereof, and control logic configured to detect internal bus transactions indicating the allocation and de-allocation of cache lines and, in response, generate bus transactions, each containing cache coherency information indicating cache line that has been allocated or de-allocated; and    a remote device having a remote cache directory indicative of contents of the cache residing on the processor, a castout buffer indicating cache lines that have been or will be castout from the processor cache, and coherency logic configured to: 
 update the remote cache directory, based on cache coherency information contained in the external bus transactions generated by the processor control logic, to reflect allocated and de-allocated cache lines of the processor cache;  
 receive a memory access request issued by a graphics processing core;  
 search the remote cache directory and castout buffer for entries matching an address targeted by the request; and  
 if no matching entries are found, route the request to external memory without sending a request to the processor.  
   
     
     
         18 . The system of  claim 17 , wherein the coherency logic is further configured to: 
 if a matching entry is found, route the request to the processor; and    create an entry in an outstanding transaction buffer containing the address targeted by the request.    
     
     
         19 . The system of  claim 18 , wherein the coherency logic is further configured to: 
 copy an entry from the outstanding transaction buffer to the castout buffer, in response to receiving coherency information from the processor indicating a corresponding cache line has been or will be cast out from the cache.