Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling

Abstract

In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well.

1 - 49 . (canceled)  
   
   
       50 . An electrically erasable programmable memory device, comprising: 
 a first semiconductor layer doped with a first dopant at a first concentration;    a second semiconductor layer, adjacent the first semiconductor layer, doped with a second dopant that has an opposite electrical characteristic than the first dopant, the second semiconductor layer having a top side;    a first diffusion region and a second diffusion region embedded in the top side of the second semiconductor layer and defining a first channel region therebetween, each diffusion region being doped with the first dopant in a second concentration greater than the first concentration;    a floating gate, comprising a conductive material, disposed adjacent the first diffusion region and above the first channel region and separated therefrom by a first insulator region, the floating gates capable of storing electrical charge; and    a control gate, comprising a conductive material, disposed laterally adjacent the floating gate on at least two sides of the floating gate and separated therefrom by a vertical insulator layer, the control gate being disposed above the first channel region and separated therefrom by a second insulator region.    
   
   
       51 . The memory device of  claim 50 , wherein the first dopant has a P-type characteristic and the second dopant has an N-type characteristic.  
   
   
       52 . The memory device of  claim 50 , wherein the first dopant has an N-type characteristic and the second dopant has a P-type characteristic.  
   
   
       53 . The memory device of  claim 50 , wherein the first insulator region has a thickness that allows tunneling of charge between the floating gate and the first channel region.  
   
   
       54 . The memory device of  claim 53 , wherein the thickness is between  70  angstroms and  110  angstroms.  
   
   
       55 . The memory device of  claim 50 , wherein the vertical insulator is made from a silicon dioxide having a thickness that prevents leakage between the floating gate and the control gate.  
   
   
       56 . The memory device of  claim 50 , wherein the vertical insulator is made from an oxide-nitrite-oxide material having a thickness that prevents leakage between the floating gate and the control gate.  
   
   
       57 . The memory device of  claim 50 , wherein the control gate is wrapped by a spacer.  
   
   
       58 . The memory device of  claim 50 , wherein the second diffusion is in contact with a vertical connector, the vertical connector being separated from the control gate by a second vertical insulator.  
   
   
       59 . The memory device of  claim 58 , wherein charge is transported from the first channel region to the floating gate when a first combination of voltages is are applied to the first diffusion region, the second diffusion region, the control gate, and the second semiconductor layer.  
   
   
       60 . The memory device of  claim 59 , wherein the first combination of voltages are applied according to a method which: 
 applying a positive high voltage to the second semiconductor layer;    applying a positive high voltage to the first diffusion region;    applying zero voltage to the second diffusion region; and    applying to the control gate a positive decreasing voltage for a first time period, followed by an increasing voltage for a second time period.    
   
   
       61 . The memory device of  claim 59 , wherein the first combination of voltages are applied according to a method which comprises: 
 applying a positive voltage between  1  V and a programming voltage to the control gate;    applying a zero voltage to the first diffusion region;    applying a positive high voltage to the second diffusion region; and    applying a positive voltage between 0V to a supply voltage to the second semiconductor layer.    
   
   
       62 . The memory device of  claim 58 , wherein charge inside the floating gate can be determined when a first combination of voltages is are applied to the first diffusion region, and the control gate.  
   
   
       63 . The memory device of  claim 62 , wherein the first combination of voltages are applied according to a method which comprises: 
 applying a supply voltage to the second semiconductor layer; applying the supply voltage to the first diffusion region; and    applying a voltage between −2V and the supply voltage to the control gate.    
   
   
       64 . The memory device of  claim 50 , wherein the first diffusion is in contact with a vertical connector, the vertical connector being separated from the floating gate by a second vertical insulator.  
   
   
       65 . The memory device of  claim 64 , wherein charge is transported from the first channel region to the floating gate when a second combination of voltages are applied to the first diffusion region, the control gate, and the second semiconductor layer.  
   
   
       66 . The memory device of  claim 65 , wherein the second combination of voltages are applied according to a method which comprises: 
 applying a positive high voltage to the control gate; applying a negative voltage to the first diffusion region; and    applying a supply voltage to the second semiconductor layer.    
   
   
       67 . The memory device of  claim 65 , wherein the second combination of voltages are applied according to a method which comprises: 
 applying a positive high voltage to the control gate;    applying a negative voltage to the first diffusion region; and    applying a negative voltage to the second semiconductor layer.    
   
   
       68 . The memory device of  claim 50 , wherein charge is transported from the floating gate to the first channel area when a third combination of voltages is are applied to the second semiconductor layer, the control gate, and the first diffusion region  
   
   
       69 . The memory device of  claim 68 , wherein the third combination of voltages are applied according to a method which comprises: 
 applying a negative voltage to the control gate;    applying a high positive voltage to the second semiconductor layer; and    applying a positive high voltage to the first diffusion region.