Scalable Link-Level Flow-Control For A Switching Device

Abstract

The present invention discloses a scalable flow-control mechanism. In accordance with the present invention, there is provided a switching device for transporting packets of data, the packets being received at the switching device based on flow-control information, the device comprising a memory for storing the packets, a credit counter coupled to the memory for counting a credit number of packets departing from the memory, and a scheduler unit coupled to the credit counter for deriving the flow-control information in response to the credit number. Moreover, a switching apparatus and a method for generating flow-control information is disclosed.

1 - 15 . (canceled)  
   
   
       16 . A switching device, comprising: 
 an input for receiving a flow of data packets, the data packets being received based on flow control information; and    a memory for storing received data packets, the memory comprised of at least one row comprised of a plurality of individually addressable memory units, each memory unit having associated therewith a credit counter and the at least one row of memory units having associated therewith a reception scheduler having inputs coupled to outputs of the credit counters, said reception scheduler having an output providing the flow control information based at least on the outputs of the credit counters.    
   
   
       17 . The switching device of  claim 16 , further comprising a memory occupancy counter having an output coupled to said reception scheduler, where the flow control information is also based on the memory occupancy counter, and where the flow control information comprises information to specify one of said plurality of memory units in which to store a data packet.  
   
   
       18 . The switching device of  claim 16 , where credits are prioritized using one of a highest memory occupancy first (HMF) procedure intended to maintain as active existing flows or by using a highest memory vacancy first (HVF) procedure intended to support flows that make forward progress at the switch level.  
   
   
       19 . A method to operate a switching device, comprising: 
 receiving a flow of data packets based on flow control information;    storing received data packets in a memory comprised of at least one row comprised of a plurality of individually addressable memory units, each memory unit having associated therewith a credit counter and the at least one row of memory units having associated therewith a reception scheduler having inputs coupled to outputs of the credit counters; and    generating the flow control information with said reception scheduler based at least in part on the outputs of the credit counters.    
   
   
       20 . The method of  claim 19 , further comprising operating a memory occupancy counter having an output coupled to said reception scheduler, where the generated flow control information is also based on the memory occupancy counter, and where the flow control information comprises information to specify one of said plurality of memory units in which to store a data packet.  
   
   
       21 . The method of  claim 19 , further comprising prioritizing credits using one of a highest memory occupancy first (HMF) procedure intended to maintain as active existing flows, or a highest memory vacancy first (HVF) procedure intended to support flows that make forward progress at the switch level.  
   
   
       22 . A switching apparatus, comprising: 
 an input for receiving data packets, the data packets being received based on flow control information;    a memory for storing received data packets, the memory comprised of at least one row comprised of a plurality of individually addressable memory units, each memory unit having associated therewith a credit counter and the at least one row of memory units having associated therewith a reception scheduler having inputs coupled to outputs of the credit counters, said reception scheduler having an output providing the flow control information based at least on the outputs of the credit counters and further specifying one of said plurality of memory units in which to store a data packet; and    a memory occupancy counter having an output coupled to said reception scheduler, where the flow control information is also based on the memory occupancy counter.    
   
   
       23 . The switching apparatus as in  claim 22 , where credits are prioritized using one of a highest memory occupancy first (HMF) procedure intended to maintain as active existing flows, or a highest memory vacancy first (HVF) procedure intended to support flows that make forward progress at the switch level.  
   
   
       24 . The switching apparatus as in  claim 22 , embodied in an integrated circuit.