Nonvolatile semiconductor memory device and manufacturing method thereof

Abstract

A nonvolatile semiconductor memory device includes a semiconductor substrate of a first conductivity type, a pair of source and drain diffusion regions of a second conductivity type oppositely formed on a surface of the semiconductor substrate, and a stacked structure having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source and drain diffusion regions. An edge of the stacked structure in the vicinity of the source region is formed away from a junction position between the source diffusion region and the channel region.

1 . A nonvolatile semiconductor memory device comprising:
 a semiconductor substrate of a first conductivity type;   a pair of a source diffusion region and a drain diffusion region of a second conductivity type oppositely formed on a surface of the semiconductor substrate; and   a stacked structure having a gate insulating film, a charge accumulation film, an interlayer insulating film and a control gate which are formed in order on a channel region of the surface of the semiconductor substrate interposed between the source diffusion region and the drain diffusion region, an edge of the stacked structure in the vicinity of the source region being formed away from a junction position between the source diffusion region and the channel region.   
     
     
         2 . The device according to  claim 1 , wherein a diffusion depth of the source diffusion region is shallower than that of the drain region. 
     
     
         3 . The device according to  claim 1 , wherein a width of the source diffusion region is formed to be less than a width of the drain diffusion region in a gate length direction of the control gate. 
     
     
         4 . The device according to  claim 3 , wherein a lightly-doped impurity region of the second conductivity type, whose impurity concentration is lower than those of the source diffusion region and the drain diffusion region, is formed between the drain diffusion region and the channel region. 
     
     
         5 . The device according to  claim 1 , wherein a highly-doped impurity region of the first conductivity type, whose impurity concentration is higher than that of the substrate, is formed in the channel region adjacent to the source region around an edge of the stacked structure. 
     
     
         6 . The device according to  claim 5 , wherein a width of the source diffusion region is formed to be less than a width of the drain diffusion region in a gate length direction of the control gate. 
     
     
         7 . The device according to  claim 1 , wherein a lightly-doped impurity region of the second conductivity type, whose impurity concentration is lower than those of the source diffusion region and the drain diffusion region, is formed between the drain diffusion region and the channel region. 
     
     
         8 . The device according to  claim 1 , wherein the charge accumulation film includes polysilicon. 
     
     
         9 . The device according to  claim 1 , wherein the charge accumulation film includes silicon nitride. 
     
     
         10 . A method of manufacturing a nonvolatile semiconductor memory device, the method comprising:
 forming a stacked film by stacking in order a gate insulating layer, a charge accumulation layer, a first interlayer insulating layer and a control gate layer on a semiconductor substrate of a first conductivity type;   by selectively etching the stacked film, forming, at regular intervals in one predetermined direction, a plurality of stacked structures having gate insulating films, charge accumulation films, first interlayer insulating films and control gates, while alternately forming a source planned region and a drain planned region with one of the stacked structures interposed therebetween on the semiconductor substrate;   forming a second interlayer insulating film to cover the plurality of stacked structures;   narrowing an exposed surface of the source planned region by processing the second interlayer insulating film such that sidewall insulating films are formed only on side surfaces of the stacked structures along the source planned region; and   forming a source diffusion region in the source planned region and a drain diffusion region in the drain planned region, by ion-implanting impurities of a second conductivity type perpendicularly to an upper surface of the semiconductor substrate with the stacked structures and the sidewall insulating films used as masks.   
     
     
         11 . A method of manufacturing a nonvolatile semiconductor memory device, the method comprising:
 forming a stacked layer by stacking in order a gate insulating layer, a charge accumulation layer, a first interlayer insulating layer and a control gate layer on a semiconductor substrate of a first conductivity type;   by selectively etching the stacked layer, arranging in a predetermined direction a plurality of stacked structures having gate insulating films, charge accumulation films, first interlayer insulating films and control gates, while alternately forming a source planned region and a drain planned region with one of the stacked structures interposed therebetween on the semiconductor substrate; and   forming a source diffusion region and a drain diffusion region, which are of a second conductivity type, along the predetermined direction on the surface of the semiconductor substrate by ion implantation of impurities of the second conductivity type using the stacked structures as masks, such that a depth of the source diffusion region is shallower than that of the drain diffusion region.   
     
     
         12 . The method according to  claim 11 , wherein
 said forming a source diffusion region and a drain diffusion region includes:   forming a second interlayer insulating film to bury the plurality of stacked structures;   removing the second interlayer insulating film on the drain planned region;   leaving the second insulating film on the source planned region at a desired height; and   forming the depth of the source diffusion region shallower than that of the drain diffusion region, by ion-implanting impurities of the second conductivity type perpendicularly to an upper surface of the semiconductor substrate, while interposing the second interlayer insulating film left only on the source planned region.   
     
     
         13 . The method according to  claim 11 , wherein
 said arranging a plurality of stacked structures in a predetermined direction includes:   arranging the stacked structures such that the source planned region having a small space and the drain planned region having a large space are alternately arranged in the predetermined direction, and   said forming the source diffusion region and the drain diffusion region includes:   forming the second interlayer insulating film so as to cover the plurality of stacked structures, to bury the source planned region and to line the drain planned region and inner surfaces of the stacked structures adjacent thereto;   providing an opening in the second interlayer insulating film on the drain planned region; and   forming the depth of the source diffusion region shallower than that of the drain diffusion region, by ion-implanting impurities of the second conductivity type perpendicularly to an upper surface of the semiconductor substrate, while interposing the second interlayer insulating film deposited on the source planned region.   
     
     
         14 . The method according to  claim 11 , wherein
 said arranging a plurality of stacked structures in a predetermined direction includes:   arranging the stacked structures such that the source planned region having a small space and the drain planned region having a large space are alternately arranged in the predetermined direction, and   said forming the source diffusion region and the drain diffusion region includes:   forming the second interlayer insulating film so as to cover the plurality of stacked structures, to bury the source planned region and to line the drain planned region and inner surfaces of the stacked structures adjacent thereto;   providing an opening in the second interlayer insulating film in the drain planned region;   ion-implanting impurities of the second conductivity type in a low concentration and obliquely with respect to an upper surface of the semiconductor substrate from two directions including a direction running from the drain planned region to the source planned region and a direction opposite thereto, such that a lightly-doped impurity region is formed only in the vicinity of the boundary between the stacked structures and the drain planned region; and   forming the source diffusion region in the source planned region, while forming the drain diffusion region in the drain planned region so as to adjoin the lightly-doped impurity region, by ion-implanting the impurities of the second conductivity type perpendicularly to the upper surface of the semiconductor substrate.   
     
     
         15 . A method of manufacturing a nonvolatile semiconductor memory device, the method comprising:
 forming a stacked layer by stacking in order a gate insulating layer, a charge accumulation layer, a first interlayer insulating layer and a control gate layer on a semiconductor substrate of a first conductivity type;   by selectively etching the stacked layer, arranging in one predetermined direction a plurality of stacked structures having gate insulating films, charge accumulation films, first interlayer insulating films and control gates, while alternately forming a source planned region and a drain planned region with one of the stacked structures interposed therebetween on the semiconductor substrate;   forming a highly-doped impurity region of the first conductivity type having a concentration higher than that of the semiconductor substrate only in the vicinity of a boundary between the stacked structures and the source planned region, by implanting impurity ions of the first conductivity type in a high concentration and obliquely with respect to an upper surface of the semiconductor substrate in a direction running from the source planned region to the drain planned region; and   forming the source diffusion region in the source planned region so as to adjoin the highly-doped impurity region, while forming the drain diffusion region in the drain planned region, by ion-implanting impurities of the second conductivity type perpendicularly to the upper surface of the semiconductor substrate.   
     
     
         16 . The method according to  claim 15 , wherein
 said forming highly-doped impurity region of the first conductivity type includes:   forming an ion implantation blocking mask on the drain planned region; and   implanting impurity ions of the second conductivity type obliquely with respect to the upper surface of the semiconductor substrate from two directions including a direction running from the source planned region to the drain planned region and a direction opposite thereto.   
     
     
         17 . The method according to  claim 15 , wherein
 said forming the highly-doped impurity region of the first conductivity type includes:   forming a second interlayer insulating film to cover the plurality of stacked structures, so as to bury the drain planned region having a small space and to line the source planned region having a large space and sidewalls of the stacked structures adjacent thereto;   providing an opening in the second interlayer insulating film on the source planned region; and   implanting impurity ions of the second conductivity type obliquely with respect to an upper surface of the semiconductor substrate from two directions including a direction running from the source planned region to the drain planned region and a direction opposite thereto.   
     
     
         18 . A method of manufacturing a nonvolatile semiconductor memory device, the method comprising:
 forming a stacked layer by stacking in order a gate insulating layer, a charge accumulation layer, an interlayer insulating layer and a control gate layer on a semiconductor substrate of a first conductivity type;   by selectively etching the stacked layer, arranging in one predetermined direction a plurality of stacked structures having gate insulating films, charge accumulation films, first interlayer insulating films and control gates, while alternately forming a source planned region and a drain planned region with one of the stacked structures interposed therebetween on the semiconductor substrate;   forming a lightly-doped impurity region of a second conductivity type only in the vicinity of a boundary between the stacked structures and the drain planned region, by implanting impurity ions of the second conductivity type obliquely with respect to an upper surface of the semiconductor substrate; and   forming the source diffusion region in the source planned region and the drain diffusion region in the drain planned region so as to adjoin the lightly-doped impurity region, by ion-implanting impurities of the second conductivity type perpendicularly to the upper surface of the semiconductor substrate.   
     
     
         19 . The method according to  claim 18 , wherein
 said forming the lightly-doped impurity region includes:   forming an ion implantation blocking mask only on the source planned region;   forming the lightly-doped impurity region by ion-implanting impurities of the second conductivity type in a low concentration obliquely with respect to the upper surface of the semiconductor substrate from two directions including a direction running from the source planned region to the drain planned region and a direction opposite thereto after said forming an ion implantation blocking mask; and   forming the source diffusion region and the drain diffusion region such that the drain diffusion region adjoins the lightly-doped impurity region, by ion-implanting impurities of the second conductivity type having a concentration higher than the low concentration perpendicularly to the upper surface of the semiconductor substrate after removal of the ion implantation blocking mask.   
     
     
         20 . The method according to  claim 18 , wherein
 said forming a lightly-doped impurity region includes:   forming the second interlayer insulating film so as to cover the plurality of stacked structures, bury the source planned region having a small space, and line the drain planned region having a large space and inner surfaces of the stacked structures adjacent thereto;   forming a lightly-doped impurity region only in the vicinity of the boundary between the drain planned region and the stacked structures, by ion-implanting impurities of the second conductivity type in a low concentration obliquely with respect to the upper surface of the semiconductor substrate from two directions including a direction running from the drain planned region to the source planned region and a direction opposite thereto; and   forming the source diffusion region and the drain diffusion region such that the drain region adjoins the lightly-doped impurity region, by ion-implanting impurities of the second conductivity type having a concentration higher than the low concentration perpendicularly to the upper surface of the semiconductor substrate.