Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device which can effectively suppress a short channel effect and junction leakage is provided. A semiconductor device includes a field effect transistor. The field effect transistor includes a first semiconductor region of a first conductivity type, a gate electrode formed on a gate insulating film, and source and drain electrodes. The field effect transistor also includes second semiconductor regions of a second conductivity type. The field effect transistor further includes third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region and formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions, and side wall insulating films formed on both the side surfaces of the gate electrode. The source electrode and the drain electrode are separated from the side wall insulating films.

1 . A semiconductor device comprising a field effect transistor including: 
 a first semiconductor region of a first conductivity type having a surface portion on which a channel region is formed;    a gate electrode formed on the channel region;    a gate insulating film in between the gate electrode and the channel region;    a source electrode and a drain electrode formed on both the sides of the channel region;    second semiconductor regions of a second conductivity type formed between the source electrode and the channel region and between the drain electrode and the channel region;    third semiconductor regions of the second conductivity type formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions and having an impurity concentration higher than that of the second semiconductor region; and    sidewall insulating films formed on both the side surfaces of the gate electrode,    the side wall insulating films being separated from the source electrode and the drain electrode.    
     
     
         2 . The semiconductor device according to  claim 1 , wherein a distance of separation between the side wall insulating film and the source electrode and between the side wall insulating film and the drain electrode is longer than 0 and not more than 30 nm.  
     
     
         3 . The semiconductor device according to  claim 1 , wherein an impurity concentration in interfaces between the third semiconductor region and the source and drain electrode is not less than 8×10 19  and not more than 5×10 20  atoms/cm 3 , 
 an impurity concentration in the third semiconductor region at a depth of 20 nm from the interfaces between the third semiconductor region and the source and drain electrode is not more than 1/10 an impurity concentration in the interfaces between the third semiconductor region and the source and drain electrode,    the second semiconductor region has a maximum impurity concentration in a gate insulating film interface, and the maximum impurity concentration is not more than ½ the impurity concentration in the interfaces between the third semiconductor region and the source and drain electrode, and    an impurity concentration of the second semiconductor region at a depth of 30 nm from the gate insulating film interface is not more than 1/10 the impurity concentration in the gate insulating film interface in the second semiconductor region.    
     
     
         4 . The semiconductor device according to  claim 1 , wherein a gate length of the gate electrode is not more than 80 nm, 
 an equivalent physical oxide thickness (EOT) of the gate insulating film is not more than 4 nm, and    a film thickness of the side wall insulating film is not more than 10 nm.    
     
     
         5 . The semiconductor device according to  claim 1 , wherein a fourth semiconductor region of the first conductivity type having an impurity concentration higher than that of the first semiconductor region is formed between the second semiconductor region and the first semiconductor region.  
     
     
         6 . The semiconductor device according to  claim 1 , wherein a fifth semiconductor region of the second conductivity type is formed between a bottom of the third semiconductor region and the first semiconductor region.  
     
     
         7 . The semiconductor device according to  claim 1 , wherein the side wall insulating film is a silicon nitride film, and an upper-layer film of the side wall insulating film is a silicon oxide film.  
     
     
         8 . The semiconductor device according to  claim 1 , wherein the first to third semiconductor regions are made of silicon.  
     
     
         9 . The semiconductor device according to  claim 1 , wherein the field effect transistor is an n-channel MIS field effect transistor, and impurities in the second and third semiconductor regions are As.  
     
     
         10 . The semiconductor device according to  claim 1 , wherein the source electrode and the drain electrode are made of nickel silicide (NiSi).  
     
     
         11 . A method of manufacturing a semiconductor device, comprising: 
 forming a gate insulating film on a first semiconductor region of a first conductivity type;    forming a gate electrode on the gate insulating film;    forming side wall insulating films on both side surfaces of the gate electrode;    ion-implanting an impurity in the first semiconductor region by using the gate electrode and the side wall insulating film as masks to form second semiconductor regions of a second conductivity type;    forming second side wall insulating films on both side surfaces of the side wall insulating film; and    siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second semiconductor region to form a source electrode and a drain electrode, and forming third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region in interfaces between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions by segregation from silicide.    
     
     
         12 . The method according to  claim 11 , wherein in forming the side wall insulating film, an amount of substrate etching is not more than 8 nm.  
     
     
         13 . The method according to  claim 11 , wherein the first to third semiconductor regions are made of silicon.  
     
     
         14 . The method according to  claim 11 , wherein the impurity is As, and the silicide is nickel silicide (NiSi).  
     
     
         15 . A method of manufacturing a semiconductor device, comprising: 
 forming a gate insulating film on a first semiconductor region of a first conductivity type;    forming a gate electrode on the gate insulating film;    forming side wall insulating films each having a footing-bottom shape at a lower surface side thereof on both side surfaces of the gate electrode;    ion-implanting an impurity in the first semiconductor region by using the gate electrode and the side wall insulating film as masks to form second semiconductor regions of a second conductivity type; and    siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second semiconductor region to form a source electrode and a drain electrode, and forming third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region in interfaces between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions by segregation from silicide.    
     
     
         16 . The method according to  claim 15 , wherein in forming the side wall insulating film, an amount of substrate etching is not more than 8 nm.  
     
     
         17 . The method according to  claim 15 , wherein the first to third semiconductor regions are made of silicon.  
     
     
         18 . The method according to  claim 15 , wherein the impurity is As, and the silicide is nickel silicide (NiSi).  
     
     
         19 . A method of manufacturing a semiconductor device, comprising: 
 forming a gate electrode on a part of a first semiconductor region of a first conductivity type, a gate insulating film in between the gate electrode and the first semiconductor region;    depositing an insulating film serving as a side wall insulating film of the gate electrode;    etching the insulating film serving as the side wall insulating film by anisotropic etching not to expose an underlying layer;    ion-implanting an impurity in the first semiconductor region from above the insulating film serving as the side wall insulating film to form second semiconductor regions of a second conductivity type serving as extension regions of a source and a drain;    etching the insulating film serving as the side wall insulating film which is etched not to expose the underlying layer to form side wall insulating films each having a footing-bottom shape at a lower surface side thereof on both side surfaces of the gate electrode; and    siliciding a part of the second semiconductor region of the second conductivity type to a region deeper than the second semiconductor region to form a source electrode and a drain electrode, and forming third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region in interfaces between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions by segregation from silicide.    
     
     
         20 . The method according to  claim 19 , wherein the first to third semiconductor regions are made of silicon, the impurity is As, and the silicide is nickel silicide (NiSi).