Method for reducing defects after a metal etching in semiconductor devices

Abstract

The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.

1 - 7 . (canceled)  
   
   
       8 . A semiconductor device comprising: 
 a semiconductor layer;    at least one conductive layer adjacent the semiconductor layer;    an antireflection coating (ARC) layer adjacent the at least one conductive layer, the ARC layer including microfissures therein; and    a dielectric covering layer on the ARC layer and filling and covering the microfissures in the ARC layer.    
   
   
       9 . A semiconductor device according to  claim 8 , wherein the thickness of the dielectric covering layer is less than 200 Å.  
   
   
       10 . A semiconductor device according to  claim 8 , wherein said dielectric covering layer comprises silicon oxide.  
   
   
       11 . A semiconductor device according to  claim 8 , wherein said at least one conductive layer comprises at least one metal layer.  
   
   
       12 . A semiconductor device according to  claim 11 , wherein said at least one metal layer comprises aluminum.  
   
   
       13 . A semiconductor device according to  claim 11 , wherein said at least one metal layer comprises an aluminum-alloy.  
   
   
       14 . A semiconductor device according to  claim 8 , further comprising an auxiliary ARC layer between said ARC layer and said dielectric covering layer.  
   
   
       15 . A semiconductor device comprising: 
 a semiconductor layer;    at least one metal layer adjacent the semiconductor layer;    an antireflection coating (ARC) layer adjacent the at least one metal layer, the ARC layer including microfissures therein; and    a silicon oxide layer on the ARC layer and filling and covering the microfissures in the ARC layer.    
   
   
       16 . A semiconductor device according to  claim 15 , wherein the thickness of the dielectric covering layer is less than 200 Å.  
   
   
       17 . A semiconductor device according to  claim 15 , wherein said at least one metal layer comprises aluminum.  
   
   
       18 . A semiconductor device according to  claim 15 , wherein said at least one metal layer comprises an aluminum-alloy.  
   
   
       19 . A semiconductor device according to  claim 15 , further comprising an auxiliary ARC layer between said ARC layer and said silicon oxide layer.  
   
   
       20 . A semiconductor device comprising: 
 a semiconductor layer;    at least one conductive layer adjacent the semiconductor layer;    an antireflection coating (ARC) layer adjacent the at least one conductive layer, the ARC layer including microfissures therein; and    a silicon oxide layer on the ARC layer and filling and covering the microfissures in the ARC layer, said silicon oxide layer having a thickness of less than 200 Å.    
   
   
       21 . A semiconductor device according to  claim 20 , wherein said at least one conductive layer comprises at least one metal layer.  
   
   
       22 . A semiconductor device according to  claim 21 , wherein said at least one metal layer comprises aluminum.  
   
   
       23 . A semiconductor device according to  claim 21 , wherein said at least one metal layer comprises an aluminum-alloy.  
   
   
       24 . A semiconductor device according to  claim 20 , further comprising an auxiliary ARC layer between said ARC layer and said silicon oxide layer.