Data bus power down for low power lcd source driver

Abstract

The invention provides solutions to solve the power consumption of the image data buses of an LCD source driver. With a bus buffer provided in one embodiment of the invention, a first image data buses are divided into several groups. Each group of image data buses is dispatched by the bus buffer. It is possible in one embodiment of the invention that some groups are active when the others are passive. Therefore, unnecessary power consumption is cut off. Despite the power saved by the management of the bus buffer, the parasitic capacitance of each group of image data buses is much smaller than that of the image data buses in the prior art. Moreover, the management of the bus buffer can depend upon the layout patterns or the layout locations of circuit components so that the driving strength of the bus buffer may be modified according to the layout pattern or the layout locations.

1 . A source driver circuit for driving an LCD panel, comprising:
 a plurality of shift registers having a plurality of first outputs;   a line buffer having at least one bus buffer to drive a portion of an image data bus depending on a control signal.   
     
     
         2 . The source driver circuit according to  claim 1  further comprising:
 a D/A converter to convert a plurality of second outputs from the line buffer;   a buffer to generate a driving current;   a plurality of gamma voltages coupled with said D/A converter; and   a level shifter to convert a plurality of said second outputs to corresponding voltage levels wherein said line buffer has multiple channel units coupled with said image data bus for different colors.   
     
     
         3 . The source driver circuit according to  claim 1 , further comprising:
 an output multiplexer to synchronize said driving current of said buffer.   
     
     
         4 . The source driver circuit according to  claim 1 , wherein said shift registers are connected in serial and triggered by a clock signal. 
     
     
         5 . The source driver circuit according to  claim 1 , wherein said line buffer receives the outputs from said shift registers sequentially in time scale. 
     
     
         6 . The source driver circuit according to  claim 2 , wherein each of said channel units comprises at least one register being able to keep image data temporarily. 
     
     
         7 . The source driver circuit according to  claim 1  wherein said image data bus comprises a red data bus, a green data bus and a blue data bus. 
     
     
         8 . The source driver circuit according to  claim 1  wherein said bus buffer comprises at least one multiplexer. 
     
     
         9 . The source driver circuit according to  claim 1 , wherein said bus buffer comprises at least one tri-state buffer. 
     
     
         10 . The source driver circuit according to  claim 1 , wherein said bus buffer comprises at least one NAND logic circuit and one inverter. 
     
     
         11 . The source driver circuit according to  claim 1 , wherein said bus buffer drives two portions of an image data bus separately. 
     
     
         12 . The source driver circuit according to  claim 1 , wherein said bus buffer selects to drive which portion of an image data bus according to at least one enable signal. 
     
     
         13 . The source driver circuit according to  claim 12 , wherein said enable signal is determined according to at least one timing signal generated by said shift registers. 
     
     
         14 . The source driver circuit according to  claim 12 , wherein said enable signal is determined according to a counter triggered by a clock signal. 
     
     
         15 . A source driver circuit or driving an LCD panel, comprising:
 at least one bus buffer to drive a portion of an image data bus;   a plurality of channel units to record image data; and   a plurality of shift registers to generate timing signals coupled with said channel units.   
     
     
         16 . The source driver circuit according to  claim 15 , further comprising:
 a control circuit outputting at least one enable signal to said bus buffer according to said timing signals.   
     
     
         17 . The source driver circuit according to  claim 15 , further comprising:
 a control circuit outputting at least one enable signal to said bus buffer according to a counter triggered by a clock signal.   
     
     
         18 . The source driver circuit according to  claim 15 , wherein said bus buffer drives two portions of an image data bus separately. 
     
     
         19 . A source driver circuit for driving an LCD panel, comprising:
 a line buffer having at least one bus buffer to drive a portion of an image data bus;   a plurality of channel units to record image data;   a plurality of shift registers to generate timing signals coupled with said channel units; and a D/A converter to convert a plurality of outputs from said line buffer.   
     
     
         20 . The source driver circuit according to  claim 19 , further comprising:
 a plurality of gamma voltages coupled with said D/A converter; and   a level shifter converting a plurality of said outputs from said line buffer to corresponding voltage levels.   
     
     
         21 . The source driver circuit according to  claim 19 , further comprising:
 an output multiplexer to synchronize driving of said line buffer.   
     
     
         22 . The source driver circuit according to  claim 19 , wherein said line buffer receives the outputs from said shift registers sequentially in time scale. 
     
     
         23 . The source driver circuit according to  claim 19 , wherein each of said channel units comprise at least one register being able to keep image data temporarily. 
     
     
         24 . The source driver circuit according to  claim 19 , wherein said image data bus comprises a red data bus, a green data bus and a blue data bus. 
     
     
         25 . The source driver circuit according to  claim 19 , wherein said bus buffer comprises at least one multiplexer. 
     
     
         26 . The source driver circuit according to  claim 19 , wherein said bus buffer comprises at least one tri-state buffer. 
     
     
         27 . The source driver circuit according to  claim 19 , wherein said bus buffer comprises at least one NAND logic circuit and one inverter. 
     
     
         28 . The source driver circuit according to  claim 19 , further comprising:
 a control circuit outputting at least one enable signal to said bus buffer.   
     
     
         29 . The source driver circuit according to  claim 28 , wherein said control circuit is controlled by at least one timing signal generated by said shift registers. 
     
     
         30 . The source driver circuit according to  claim 28 , wherein said control circuit comprises a counter. 
     
     
         31 . The source driver circuit according to  claim 19 , wherein said bus buffer drives two portions of an image data bus separately.