Nonvolatile memory apparatus

Abstract

A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.

1 - 12 . (canceled)  
   
   
       13 . A memory device comprising: 
 a plurality of memory cells;    a plurality of data lines, each of which is coupled to a corresponding memory cells; and    a plurality of data latches, each of which is coupled to corresponding data line,    wherein in a read operation, the data latches receive data stored in ones of the memory cells via the data lines, a first data latch transfers data therein to a second data latch, and then the second data latch outputs data transferred from the first data latch to outside instead of the first data latch.    
   
   
       14 . A memory device according to  claim 13 , 
 wherein in the read operation, data received from the memory cell in the second latch is overwritten by the data transferred from the first data latch.    
   
   
       15 . A memory device according to  claim 14 , further comprising an address register to store information for addressing the first data latch and the second data latch.  
   
   
       16 . A memory device comprising: 
 a plurality of memory cells;    a plurality of data lines, each of which is coupled to corresponding memory cells; and    a plurality of data latches, each of which is coupled to a corresponding data line,    wherein in a write operation, a first data latch receives data from outside, the first data latch transfers data therein to a second data latch, and then data stored in the second data latch is stored into one of the memory cells coupled to the second data latch via the corresponding data line.    
   
   
       17 . A memory device according to  claim 16 , 
 wherein in the write operation, the second data latch does not receive data directly from outside.