Method and Apparatus for Buffering Bi-Directional Open Drain Signal Lines

Abstract

A buffer system includes a logic adjusting circuit for translating a first logic level of a first component to a second logic level of a second component. The first and second logic level values are substantially different, and the buffer system has no directional control signal. A method of interfacing at least two components with different logic voltage requirements on a single bus without a separate directional control signal includes initializing a buffering circuit, activating the buffering circuit, transferring data through the buffering circuit, and deactivating the buffering circuit. A method of implementing a bi-directional interface between at least two devices interfaced on a bus includes providing a plurality of logic components interconnected to transfer data through the bus, and transferring data through the bus from a first device to a second device. The direction of data transfer is determined without a separate directional control signal.

1 . A method of interfacing at least two components with different logic voltage requirements on a single bus without a separate directional control signal, the different logic voltage requirements having substantially different values, the method comprising: 
 initializing a buffering circuit including providing power to the buffering circuit and asserting a start signal;    activating the buffering circuit including de-asserting the start signal;    transferring data through the buffering circuit according to a data transfer protocol; and    deactivating the buffering circuit.    
   
   
       2 . The method as claimed in  claim 1 , wherein the data transfer protocol includes a start protocol, a transfer protocol, and a stop protocol.  
   
   
       3 . The method as claimed in  claim 2 , wherein the start protocol includes a start bit, the start bit indicating a beginning of a data transfer, and an internal timing signal.  
   
   
       4 . The method as claimed in  claim 3 , wherein the start bit is logic 0 and the internal timing signal is a clock signal changing from logic 1 to logic 0.  
   
   
       5 . The method as claimed in  claim 2 , wherein the transfer protocol includes an internal timing signal being logic 0.  
   
   
       6 . The method as claimed in  claim 2 , wherein the stop protocol includes a stop bit and an internal timing signal.  
   
   
       7 . The method as claimed in  claim 6 , wherein the stop bit is logic 1 and the internal timing signal is a clock signal changing from logic 0 to logic 1.  
   
   
       8 . The method as claimed in  claim 1 , wherein the components are bi-directional open drain circuits.