Facilitating Inter-DSP Data Communications

Abstract

A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

1 . A method for facilitating inter-digital signal processing (DSP) data communications comprising the steps of: 
 reading a first data structure associated with a block of local memory in a first DSP processor core in a complex comprising a plurality of DSP processor cores, wherein said first data structure comprises a first source address indicating a first address of where data is stored in said local memory of said first DSP processor core, wherein said first data structure further comprises an indication of a size of a block of memory, wherein said first data structure further comprises a first destination address indicating a second address of where data is to be stored in a local memory of a second DSP processor core; and    initiating a transfer of moving data said size of said block of memory located in said first source address in said local memory of said first DSP processor core to said first destination address in said local memory of said second DSP processor core.    
   
   
       2 - 10 . (canceled)  
   
   
       11 . A computer program product embodied in a machine readable medium for facilitating inter-digital signal processing (DSP) data communications comprising the programming steps of: 
 reading a first data structure associated with a block of local memory in a first DSP processor core in a complex comprising a plurality of DSP processor cores, wherein said first data structure comprises a first source address indicating a first address of where data is stored in said local memory of said first DSP processor core, wherein said first data structure further comprises an indication of a size of a block of memory, wherein said first data structure further comprises a first destination address indicating a second address of where data is to be stored in a local memory of a second DSP processor core; and    initiating a transfer of moving data said size of said block of memory located in said first source address in said local memory of said first DSP processor core to said first destination address in said local memory of said second DSP processor core.    
   
   
       12 - 20 . (canceled)  
   
   
       21 . A system, comprising: 
 a plurality of digital signal processing (DSP) units;    a direct memory access controller coupled to said plurality of DSP processor cores, wherein said direct memory access controller comprises: 
 a memory unit operable for storing a computer program for facilitating inter-DSP data communications; and  
 a processor coupled to said memory unit, wherein said processor, responsive to said computer program, comprises: 
 circuitry operable for reading a first data structure associated with a block of local memory in a first DSP processor core, wherein said first data structure comprises a first source address indicating a first address of where data is stored in said local memory of said first DSP processor core, wherein said first data structure further comprises an indication of a size of a block of memory, wherein said first data structure further comprises a first destination address indicating a second address of where data is to be stored in a local memory of a second DSP processor core; and  
 circuitry operable for initiating a transfer of moving data said size of said block of memory located in said first source address in said local memory of said first DSP processor core to said first destination address in said local memory of said second DSP processor core.  
 
   
   
   
       22 - 30 . (canceled)