Semiconductor Device and Method for Manufacturing the Same

Abstract

A semiconductor device and method for manufacturing the same is provided, capable of gap-filling a copper metal wiring while minimizing void generation. A semiconductor device according to an embodiment includes a copper sulfide layer formed on a first barrier metal formed in a via and trench; and a via plug and an upper metal wiring formed in the via hole and the trench, respectively, on the copper sulfide layer and an exposed lower metal wiring.

1 . A semiconductor device comprising:
 a first barrier metal formed on an interlayer dielectric layer;   a copper sulfide layer formed on the first barrier metal; and   a copper wiring formed on the copper sulfide layer.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein the interlayer dielectric layer comprises a first interlayer dielectric layer including a via hole and a second interlayer dielectric layer formed above the first interlayer dielectric layer including a trench in contact with the via hole of the first interlayer dielectric layer; and
 wherein the copper wiring comprises a via plug formed in the via hole and an upper metal wiring formed in the trench.   
   
   
       3 . The semiconductor device according to  claim 2 , further comprising:
 a lower interlayer dielectric layer including a lower metal wiring; and   a capping film formed on the lower metal wiring while selectively exposing the lower metal wiring to the via plug.   
   
   
       4 . The semiconductor device according to  claim 3 , wherein the first interlayer dielectric layer is formed on the capping film. 
   
   
       5 . The semiconductor device according to  claim 3 , wherein the first barrier metal does not contact a top surface of the exposed lower metal wiring. 
   
   
       6 . The semiconductor device according to  claim 3 , wherein the lower metal wiring is one selected from the group consisting of Cu, Al, Ag, Au, and W. 
   
   
       7 . The semiconductor device according to  claim 3 , wherein the lower interlayer dielectric layer is one selected from the group consisting of a TEOS-CVD, a plasma enhanced chemical vapor deposition (PECVD)-SiO 2 , a PECVD-SiON, a BPSG, a CVD- SiO 2  film, and a phospho silicate glass (CVD-PSG). 
   
   
       8 . The semiconductor device according to  claim 1 , the first barrier metal comprises TaN. 
   
   
       9 . The semiconductor device according to  claim 1 , wherein the first barrier metal comprises TiN. 
   
   
       10 . The semiconductor device according to  claim 1 , wherein the copper sulfide is a copper sulfide layer (Cu 2 S 4 ) comprising a sulfur monolayer. 
   
   
       11 . A method for manufacturing a semiconductor device comprising the steps of:
 forming a via hole and a trench in contact with the via hole by etching a first interlayer dielectric layer and a second interlayer dielectric layer;   forming a first barrier metal on the etched first interlayer dielectric layer and second interlayer dielectric layer; and   forming a sulfide layer on the first barrier metal.   
   
   
       12 . The method according to  claim 11 , further comprising:
 forming a capping film on a lower metal wiring, wherein the first interlayer dielectric layer and the second interlayer dielectric layer are sequentially formed on the capping film; and   exposing the lower metal wiring by etching the capping film in the via hole area.   
   
   
       13 . The method according to  claim 12 , wherein forming the sulfide layer on the first barrier metal comprises:
 forming a second barrier metal including sulfur (S) on the first barrier metal; and   thermally processing the second barrier metal.   
   
   
       14 . The method according to  claim 13 , wherein the sulfide layer comprises a copper sulfide layer, the method further comprising:
 forming a via plug and an upper metal wiring by filling the via hole and the trench with copper, thereby forming the copper sulfide layer by contact of the copper with the thermally processed second barrier metal.   
   
   
       15 . The method according to  claim 13 , wherein the first barrier metal comprises TaN and the second barrier metal comprises TaS. 
   
   
       16 . The method according to  claim 13 , wherein the first barrier metal comprises TiN and the second barrier metal comprises TiS. 
   
   
       17 . The method according to  claim 13 , wherein the second barrier metal comprises 1 wt % to 4 wt % of sulfur (S). 
   
   
       18 . The method according to  claim 13 , wherein the second barrier metal is amorphous. 
   
   
       19 . The method according to  claim 13 , wherein thermally processing the second barrier metal comprises performing the thermal processing at a temperature of about 100° C. to about 300° C. 
   
   
       20 . The method according to  claim 13 , wherein thermally processing the second barrier metal comprises performing the thermal processing for about 1 minute to about 120 minutes.