Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same. The semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region within the first well, and a third well formed within the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.

1 . A semiconductor device, comprising: 
 a first well formed in a predetermined region of a semiconductor substrate;    a second well formed in a predetermined region within the first well; and    a third well formed within the first well with the third well being spaced apart from the second well at a predetermined distance,    whereby a multiple well of the semiconductor substrate comprising the sequentially formed the first well and second well, and the sequentially formed first well and third well, is formed.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the first well is formed using an N-type impurity, and the second well and the third well are formed using a P-type impurity.  
   
   
       3 . A method of manufacturing a semiconductor device, the method comprising the steps of: 
 injecting a predetermined impurity ion into a predetermined region of a semiconductor substrate, forming a first well;    etching a predetermined region of the semiconductor substrate in which the first well is formed, forming a trench;    gap-filling the trench with a polysilicon layer;    forming an impurity region in a predetermined region within the first well so that the impurity region is connected to the polysilicon layer, forming a second well comprising the polysilicon layer and the impurity region; and    performing a predetermined impurity ion implantation process to form a third well in a predetermined region within the first well so that the third well is spaced apart from the second well at a predetermined distance.    
   
   
       4 . The method of  claim 3 , comprising forming the first well by injecting an N-type impurity.  
   
   
       5 . The method of  claim 3 , further comprising the step of performing an annealing process after forming the trench.  
   
   
       6 . The method of  claim 5 , comprising performing the annealing process under a nitrogen atmosphere.  
   
   
       7 . The method of  claim 5 , comprising performing the annealing process at a temperature of 850° C. to 1100° C. for 30 minutes to 60 minutes.  
   
   
       8 . The method of  claim 3 , comprising doping the polysilicon layer with a P-type impurity.  
   
   
       9 . The method of  claim 3 , comprising forming the impurity region is formed by injecting a P-type impurity and then performing an nitrogen annealing process so that the impurity region is connected to the bottom of the polysilicon layer.  
   
   
       10 . The method of  claim 3 , comprising forming the third well by injecting a P-type impurity.