Method and apparatus to generate a clock-based transmission

Abstract

A method and apparatus are disclosed to generate and/or receive ultra-wide bandwidth (UWB) pulses using a digital clock.

1 . A method comprising: 
 receiving a direct sequence ultrawide bandwidth signal; and    extracting data from said direct sequence ultrawide bandwidth signal using said digitally produced clock signal, wherein extracting said data comprises: 
 digitally producing a clock signal;  
 delaying said digitally produced clock signal to produce a delayed clock signal, wherein said delayed clock signal is synchronized with said direct sequence ultrawide bandwidth signal; and  
 mixing said delayed clock signal with said direct sequence ultrawide bandwidth signal to obtain said data.  
   
   
   
       2 . The method of  claim 1 , wherein said direct sequence ultrawide bandwidth is a pulsed direct sequence ultrawide bandwidth signal.  
   
   
       3 . The method of  claim 1 , wherein said direct sequence ultrawide bandwidth signal is a sub-banded direct sequence ultrawide bandwidth signal.  
   
   
       4 . The method of  claim 1 , comprising: 
 forming a template signal correlated with said direct sequence ultrawide bandwidth signal; and    mixing said direct sequence ultrawide bandwidth signal with said template signal.    
   
   
       5 . The method of  claim 4 , wherein said delayed clock signal is used to form said template signal.  
   
   
       6 . The method of  claim 1 , comprising filtering said data to remove high order harmonics.  
   
   
       7 . An apparatus, comprising: 
 a digital clock to produce a digital clock signal;    a receiver to receive a direct sequence ultrawide bandwidth signal;    a variable digital delay circuit to delay said digital clock signal to produce a delayed clock signal, wherein said delayed clock signal is synchronized with said direct sequence ultrawide bandwidth signal; and    a mixer to mix said delayed clock signal with said direct sequence ultrawide bandwidth signal to obtain data.    
   
   
       8 . The apparatus of  claim 7 , wherein said direct sequence ultrawide bandwidth is a pulsed direct sequence ultrawide bandwidth signal.  
   
   
       9 . The apparatus of  claim 7 , wherein said direct sequence ultrawide bandwidth signal is a sub-banded direct sequence ultrawide bandwidth signal.  
   
   
       10 . The apparatus of  claim 7 , comprising: 
 a code generator to form a template signal correlated with said direct sequence ultrawide bandwidth signal; and    a mixer to mix said direct sequence ultrawide bandwidth signal with said template signal.    
   
   
       11 . The apparatus of  claim 10 , wherein said delayed clock signal from said variable digital delay circuit is used by said code generator to form said template signal.  
   
   
       12 . The apparatus of  claim 7 , comprising a filter to filter said data to remove high order harmonics.  
   
   
       13 . A system, comprising: 
 an antenna;    a digital clock to produce a digital clock signal;    a receiver operably coupled to said antenna to receive a direct sequence ultrawide bandwidth signal;    a variable digital delay circuit to delay said digital clock signal to produce a delayed clock signal, wherein said delayed clock signal is synchronized with said direct sequence ultrawide bandwidth signal; and    a mixer to mix said delayed clock signal with said direct sequence ultrawide bandwidth signal to obtain data.    
   
   
       14 . The system of  claim 13 , wherein said direct sequence ultrawide bandwidth is a pulsed direct sequence ultrawide bandwidth signal.  
   
   
       15 . The system of  claim 13 , wherein said direct sequence ultrawide bandwidth signal is a sub-banded direct sequence ultrawide bandwidth signal.  
   
   
       16 . The system of  claim 13 , comprising: 
 a code generator to form a template signal correlated with said direct sequence ultrawide bandwidth signal; and    a mixer to mix said direct sequence ultrawide bandwidth signal with said template signal.    
   
   
       17 . The system of  claim 16 , wherein said delayed clock signal from said variable digital delay circuit is used by said code generator to form said template signal.  
   
   
       18 . The system of  claim 13 , comprising a filter to filter said data to remove high order harmonics.