High speed transceiver with low power consumption

Abstract

High-speed and low-power consumption CMOS receivers using adaptively-regulated power supply and pseudo differential digital logic to: 1) reduce the power consumption of the transceiver; and, 2) increase the power supply rejection (PSR) during processing the data.

1 . A transceiver, comprising: 
 an input port to receive an input signal;    a first Complementary Metal-Oxide Semiconductor (CMOS) logic unit coupled with the input port to convert the input signal into a first signal of a pseudo differential digital output; and    a second Complementary Metal-Oxide Semiconductor (CMOS) logic unit coupled with the input port to convert the input signal into a second signal of the pseudo differential digital output.    
   
   
       2 . The transceiver of  claim 1 , wherein the first CMOS logic unit comprises a buffer; and wherein the second CMOS logic unit comprises an inverter.  
   
   
       3 . The transceiver of  claim 2 , wherein the buffer and the inverter receive a same signal as input generated from the input signal.  
   
   
       4 . The transceiver of  claim 1 , further comprising: 
 a common mode feedback (CMFB) circuit coupled to the first and second logic units, the CMFB circuit to adjust the first and second logic units according to a common mode detected from the pseudo differential digital output.    
   
   
       5 . The transceiver of  claim 1 , further comprising: 
 a cross couple circuit coupled to the first and second logic units, the cross couple circuit to cross couple the first and second signals to maintain opposite polarity in the pseudo differential digital output.    
   
   
       6 . The transceiver of  claim 5 , wherein the cross couple circuit comprises: 
 a first inverter connecting outputs of the first and second logic units in a first direction; and    a second inverter connecting the outputs of the first and second logic units in a second direction that is opposite to the first direction.    
   
   
       7 . The transceiver of  claim 1 , further comprising: 
 a clock synchronization circuit coupled to the first and second logic units to synchronize timing of the first and second signals of the pseudo differential digital output.    
   
   
       8 . An advanced memory buffer, comprising: 
 a pseudo differential digital logic to convert an input received from a port to a differential output; and    an adaptive power-supply regulator coupled with the pseudo differential digital logic circuit, the adaptive power-supply regulator to adjust a power supply to the pseudo differential digital logic circuit to reduce power consumption and noise.    
   
   
       9 . The advanced memory buffer of  claim 8 , further comprising: 
 a de-multiplexer to drive a parallel data link according to the differential output.    
   
   
       10 . A transceiver, comprising: 
 a Complementary Metal-Oxide Semiconductor (CMOS) pseudo differential digital logic circuit to convert an input to the transceiver into a differential digital output.    
   
   
       11 . The transceiver of  claim 10 , wherein the pseudo differential digital logic circuit includes no current mode logic.  
   
   
       12 . The transceiver of  claim 10 , further comprising: 
 an adaptive power-supply regulator coupled with the pseudo differential digital logic circuit to adaptively adjust a power supply of the pseudo differential digital logic circuit to reduce power consumption.    
   
   
       13 . The transceiver of  claim 12 , wherein the power supply of the pseudo differential digital logic circuit is adjusted according to an operating frequency of the pseudo differential digital logic circuit.  
   
   
       14 . The transceiver of  claim 12 , wherein the power supply of the pseudo differential digital logic circuit is adjusted according to fabrication process.  
   
   
       15 . The transceiver of  claim 12 , wherein the power supply of the pseudo differential digital logic circuit is adjusted according to operating temperature variation.  
   
   
       16 . The transceiver of  claim 12 , wherein the power supply of the pseudo differential digital logic circuit is adjusted according to data transmission pattern.  
   
   
       17 . The transceiver of  claim 10 , further comprising: 
 an adaptive power-supply regulator coupled with the pseudo differential digital logic circuit to adaptively adjust a power supply of the pseudo differential digital logic circuit to maintain speed.    
   
   
       18 . The transceiver of  claim 17 , further comprising: 
 a clock recovery circuit, wherein the clock recovery and the adaptive power-supply regulator share a voltage controlled oscillator.    
   
   
       19 . A transceiver, comprising: 
 a buffer to convert an input signal into a first signal of a pseudo differential digital output; and    an invert to convert the input signal into a second signal of the pseudo differential digital output.    
   
   
       20 . The transceiver of  claim 19 , further comprising: 
 a logic circuit unit coupled with the buffer and the inverter to synchronize the first and second signals of the pseudo differential digital output.