Integrated devices on a common compound semiconductor III-V wafer

Abstract

A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs.

1 . A method of fabricating an integrated III-V semiconductor structure including at least two different types of active devices comprising:
 providing a substrate;   performing an in-situ substrate cleaning process to reduce the presence of contaminants on the substrate;   growing a first epitaxial structure on the substrate;   growing a second epitaxial structure on the first epitaxial structure; and   processing the epitaxial structures to form different types of active devices.   
     
     
         2 . The method of  claim 1  including processing the epitaxial structures so that the first epitaxial structure forms at least part of a first type of device and the second epitaxial structure forms at least part of a second type of device. 
     
     
         3 . The method of  claim 2  wherein one of the first and second types of devices is a FET and the other type of device is a HBT. 
     
     
         4 . The method of  claim 2  wherein one of the first and second types of devices is a PHEMT and the other type of device is a HBT. 
     
     
         5 . The method of  claim 1  wherein performing an in-situ substrate cleaning process includes exposing the substrate to a halide-based etchant. 
     
     
         6 . The method of  claim 1  wherein performing an in-situ substrate cleaning process includes exposing the substrate to a halide-based etchant and hydrogen. 
     
     
         7 . The method of  claim 6  wherein the in-situ substrate cleaning process includes:
 exposing the substrate to a hydrogen-containing gas;   subsequently etching the substrate by exposing the substrate to a chlorine-based etchant and the hydrogen-containing gas; and   subsequently exposing the substrate to the hydrogen-containing gas only.   
     
     
         8 . The method of  claim 6  including performing the cleaning process at a temperature greater than 400° C. 
     
     
         9 . The method of  claim 8  including performing the cleaning process at a pressure in a range of between 10 Torr and atmospheric pressure. 
     
     
         10 . The method of  claim 6  including performing the cleaning process at a temperature in a range of 600-700° C. 
     
     
         11 . The method of  claim 10  including performing the cleaning process at a pressure in a range of 50-80 Torr. 
     
     
         12 . The method of  claim 6  including exposing the substrate to a halide-based etchant and hydrogen for a duration of several minutes or less. 
     
     
         13 . The method of  claim 1  wherein performing the in-situ substrate cleaning process includes exposing the substrate to AsCl 3  and AsH 3    
     
     
         14 . The method of  claim 1  wherein a dopant concentration at an interface of the substrate and the at least one epitaxial structure is between ten and hundred times less than it would be in the absence of the in-situ cleaning process. 
     
     
         15 . The method of  claim 1  wherein growing at least one epitaxial structure includes growing a layer to serve as a channel for an active device, wherein a doping profile from the channel layer to a surface of the substrate decreases substantially continuously. 
     
     
         16 . The method of  claim 1  wherein a dopant concentration at an interface of the substrate and the at least one epitaxial structure is substantially smooth. 
     
     
         17 . A semiconductor structure comprising:
 a substrate;   a first epitaxial structure disposed on top of the substrate; and   a second epitaxial structure disposed on top of the first epitaxial structure;   wherein the epitaxial structures form portions of different types of active devices and wherein an interface between the substrate and the first epitaxial structure is substantially free of contaminants.   
     
     
         18 . The semiconductor structure of  claim 17  wherein a doping profile at an interface of the substrate and the first epitaxial structure is substantially smooth. 
     
     
         19 . The semiconductor structure of  claim 17  wherein the first epitaxial structure includes a layer to serve as a channel for an active device, wherein a doping profile from the channel layer to a surface of the substrate decreases substantially continuously. 
     
     
         20 . An integrated circuit package comprising:
 a housing;   a semiconductor structure in the housing, wherein the semiconductor structure includes:
 a substrate; 
 a first epitaxial structure disposed on top of the substrate, wherein an interface between the substrate and the first epitaxial structure is substantially free of contaminants; 
 a second epitaxial structure disposed on top of the first epitaxial structure, wherein the first and second epitaxial structures form portions of different types of active devices that are electrically connected; and 
 electrical contacts for the active devices; and 
   external electrical connections electrically coupled to the contacts.   
     
     
         21 . The integrated circuit package of  claim 17  wherein the semiconductor structure further includes passive devices electrically coupled to the active devices. 
     
     
         22 . The integrated circuit package of  claim 20  wherein the housing comprises an encapsulated plastic module. 
     
     
         23 . A method of fabricating an integrated III-V compound semiconductor structure including at least two different types of active devices, the method comprising:
 providing a first III-V compound semiconductor substrate in a reactor;   growing at least two epitaxial structures for different types of devices on the first substrate while the first substrate is in the reactor;   removing the first substrate from the reactor;   coating inner surfaces of the reactor to reduce the release of contaminants from those surfaces during subsequent process steps;   subsequently providing a second III-V compound semiconductor substrate in the reactor;   growing at least two epitaxial structures for different types of devices on the second substrate while the second substrate is in the reactor; and   processing the epitaxial structures on the second substrate to form different types of active devices.   
     
     
         24 . The method of  claim 23  including processing the epitaxial structures on the second substrate so that a first epitaxial structure forms at least part of a first type of device and a second epitaxial structure forms at least part of a second type of device. 
     
     
         25 . The method of  claim 24  wherein one of the first and second types of devices is a FET and the other type of device is a HBT. 
     
     
         26 . The method of  claim 24  wherein one of the first and second types of devices is a PHEMT and the other type of device is a HBT. 
     
     
         27 . The method of  claim 23  wherein the coating comprises substantially the same material as the III-V semiconductor substrate. 
     
     
         28 . The method of  claim 27  wherein the coating is grown epitaxially. 
     
     
         29 . The method of  claim 27  wherein the coating comprises GaAs. 
     
     
         30 . The method of  claim 27  wherein the coating has a thickness of less than about 3 μm. 
     
     
         31 . The method of  claim 23  including separating the second substrate into individual integrated circuit chips each of which includes at least two different types of active devices. 
     
     
         32 . A method of fabricating an integrated III-V semiconductor device comprising:
 providing a substrate;   growing a first epitaxial structure on the substrate;   growing a second epitaxial structure on the first epitaxial structure;   growing a third epitaxial structure on top of the second epitaxial structure; and   processing the epitaxial structures to form different types of active devices.   
     
     
         33 . The method of  claim 32  wherein the first and second epitaxial structures have a composition and thickness designed for fabrication into a first semiconductor device with first operational characteristics. 
     
     
         34 . The method of  claim 33  wherein the second and third epitaxial structures have a composition and thickness designed for fabrication into a second semiconductor device with second operational characteristics. 
     
     
         35 . The method of  claim 34  wherein growing the second epitaxial structure includes growing a contact layer that is shared by the first and second semiconductor devices. 
     
     
         36 . The method of  claim 33  wherein the first semiconductor device further comprises a herterojunction bipolar transistor. 
     
     
         37 . The method of  claim 33  wherein the first semiconductor device further comprises a field effect transistor. 
     
     
         38 . The method of  claim 34  wherein the second semiconductor device comprises a herterojunction bipolar transistor. 
     
     
         39 . The method of  claim 34  wherein the second semiconductor device comprises a field effect transistor. 
     
     
         40 . The method of  claim 32  semiconductor device wherein the substrate comprises GaAs. 
     
     
         41 . The method of  claim 32  wherein growing the first epitaxial structure includes growing a low leakage buffer layer on the substrate. 
     
     
         42 . The method of  claim 41  wherein growing the buffer layer includes sequentially growing a plurality of epitaxial layers of different materials. 
     
     
         43 . The method of  claim 41  wherein growing the buffer layer includes sequentially growing a plurality of epitaxial layers of different III-V semiconductor materials. 
     
     
         44 . The method of  41  wherein growing the buffer layer includes:
 growing an undoped epitaxial AlGaAs layer on the substrate; and   growing an undoped epitaxial GaAs layer on the AlGaAs layer.   
     
     
         45 . An integrated pair of HBT and FET transistors on a common compound semiconductor III-V layer. 
     
     
         46 . An integrated pair of HBT and FET transistors sharing a common compound semiconductor III-V epitaxial layer.