Method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency

Abstract

A method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency. Independent clock signals are generated at predetermined clock frequency targets in response to control signals that are based on a determined bus clock frequency.

1 - 19 . (canceled)  
   
   
       20 . A clock circuit comprising: 
 a duration timer for continuing to a predetermined duration using a reference clock signal, the duration timer issuing a stop signal when the predetermined duration is reached;    a bus clock determining circuit, coupled to the duration timer, the bus clock determining circuit providing a bus clock determination value by monitoring a bus clock until the duration timer issues the stop signal;    a controller, coupled to the bus clock determining circuit, the controller receiving the bus clock determination value and generating independent control signals based on the determined bus clock determination value and predetermined clock frequency targets; and    a clock signal generator, coupled to the controller, for receiving the independent control signals from the controller and generating a plurality of clock signals at predetermined clock frequency targets in response to the independent control signals.    
   
   
       21 . The clock circuit of  claim 20  wherein the bus clock determining circuit further comprises a reference clock for generating the reference clock signal.  
   
   
       22 . The clock circuit of  claim 21  wherein the controller initiates the duration timer and the bus clock determining circuit and the duration timer begins to count to the predetermined duration and the bus clock determining circuit begins to count bus clock cycles.  
   
   
       23 . The clock circuit of  claim 21  wherein the controller accesses a value contained in the bus clock determining circuit for determining a bus clock frequency.  
   
   
       24 . The clock circuit of  claim 23  wherein the controller generates independent control signals based on the determined bus clock frequency and predetermined clock frequency targets based on the value of the bus clock determining circuit, valid PLL multiplier values and clock frequency maximum and minimums.  
   
   
       25 . The clock circuit of  claim 21  wherein the controller monitors whether a reset is received, re-initiates the duration timer and resets the bus clock determining circuit after the bus clock determining circuit is signaled to stop monitoring the bus clock when a reset is received and determines whether the counter value has changed.  
   
   
       26 . An application specific integrated circuit, comprising: 
 a plurality of interfaces, the interfaces providing access to asynchronous devices; and    a clock circuit for providing clocks to multiple frequency domains for transferring data between the plurality of interfaces using a single input clock of variable frequency, the clock circuit further comprising: 
 a duration timer for counting to a predetermined duration using a reference clock signal, the duration timer issuing a stop signal when the predetermined duration is reached;  
 a bus clock determining circuit, coupled to the duration timer, the bus clock determining circuit providing a bus clock determination value by monitoring a bus clock until the duration timer issues the stop signal;  
 at controller, coupled to the bus clock determining circuit, the controller receiving the bus clock determination value and generating independent control signals based on the determined bus clock determination value and predetermined clock frequency targets; and  
 a clock signal generator, coupled to the controller, for receiving the independent control signals from the controller and generating a plurality of clock signals at predetermined clock frequency targets in response to the independent control signals.  
   
   
   
       27 . The application specific integrated circuit of  claim 26  wherein the bus clock determining circuit further comprises a reference clock for generating the reference clock signal.  
   
   
       28 . The application specific integrated circuit of  claim 27  wherein the controller initiates the duration timer and the bus clock determining circuit and the duration timer begins to count to the predetermined duration and the bus clock determining circuit begins to count bus clock cycles.  
   
   
       29 . The application specific integrated circuit of  claim 28  wherein the controller accesses a value contained in the bus clock determining circuit for determining a bus clock frequency.  
   
   
       30 . The application specific integrated circuit of  claim 29  wherein the controller generates independent control signals based on the determined bus clock frequency and predetermined clock frequency targets based on the value of the bus clock determining circuit, valid PLL multiplier values and clock frequency maximum and minimums.  
   
   
       31 . The application specific integrated circuit of  claim 27  wherein the controller monitors whether a reset is received, re-initiates the duration timer and resets the bus clock determining circuit after the bus clock determining circuit is signaled to stop monitoring the bus clock when a reset is received, and determines whether the counter value has changed.  
   
   
       32 . A program storage device readable by a computer, the medium tangibly embodying one or more programs of instructions executable by the computer to perform a method for providing clocks to multiple frequency domains using a single input clock of variable frequency, the method comprising: 
 issuing a stop signal based on a comparison of a reference clock pulse count and a predetermined time,    monitoring a bus clock until the stop signal is issued to determine a bus clock frequency;    deriving independent control signals based on the determined bus clock frequency and predetermined clock frequency targets; and    generating a plurality of clock signals at the predetermined clock frequency targets in response to the derived independent control signals.    
   
   
       33 . The program storage device of  claim 32  further comprising monitoring the bus clock for a controlled duration.  
   
   
       34 . The program storage device of  claim 33  wherein the monitoring the bus clock for a controlled duration further comprises: 
 providing a reference clock to a duration timer for counting to a predetermined duration;    determining when the duration timer has counted tip to the predetermined duration; and    in response to determining that the duration timer has counted up to the predetermined duration, signaling a bus clock counter to stop monitoring the bus clock.    
   
   
       35 . The program storage device of  claim 32  further comprising returning the value contained in the bus clock counter to the controller.  
   
   
       36 . The program storage device of  claim 35  further comprising using the value contained in the bus clock counter at the controller to determine the frequency of the bus clock.  
   
   
       37 . The program storage device of  claim 32  wherein the deriving independent control signals based on the determined bus clock frequency and predetermined clock frequency targets further comprises setting internal and external clock frequencies depending on the value of a bus clock counter, valid PLL multiplier values and clock frequency maximum and minimums.  
   
   
       38 . The program storage device of  claim 34  further comprising monitoring whether a reset is received, re-initiating the duration timer and resetting the bus clock counter after the bias clock counter is signaled to stop monitoring the bus clock when a reset is received, and determining whether the counter value had changed.