Formation of high voltage transistor with high breakdown voltage

Abstract

A high voltage transistor exhibiting an improved breakdown voltage and related methods are provided. For example, a method of manufacturing an integrated circuit includes etching a poly silicon layer to provide a gate stacked above a floating gate of a flash memory cell. A source and a drain of the flash memory cell are implanted in a substrate. The poly silicon layer is etched to provide a gate of a high voltage transistor. Lightly doped drain (LDD) implants are provided in source/drain regions of the high voltage transistor in the substrate. An annealing operation is performed on the integrated circuit, wherein the annealing causes each of the LDD implants to form a graded junction in relation to a channel in the substrate between the LDD regions, and further causes sidewalls to oxidize on the gates of the flash memory cell and on the gate of the high voltage transistor.

1 - 9 . (canceled) 
   
   
       10 . An integrated circuit comprising:
 a substrate;   a flash memory cell comprising:
 a floating gate, 
 a gate stacked above the floating gate, 
 oxidized sidewalls on the gates of the flash memory cell, and 
 a source and a drain in the substrate; and 
   a high voltage transistor comprising:
 a gate, 
 oxidized sidewalls on the gate of the high voltage transistor, 
 a channel in the substrate, and 
 lightly doped drain (LDD) implants in the substrate and adjacent to the channel, wherein the LDD implants form a graded junction in relation to the channel. 
   
   
   
       11 . The integrated circuit of  claim 10 , wherein the high voltage transistor is adapted to sustain a programming voltage provided to the flash memory cell. 
   
   
       12 . The integrated circuit of  claim 10 , wherein the high voltage transistor is adapted to sustain a programming voltage greater than approximately  9 . 5  volts provided to the flash memory cell. 
   
   
       13 . The integrated circuit of  claim 10 , wherein the high voltage transistor further comprises a source and a drain adjacent to the LDD implants, wherein the source and drain of the high voltage transistor have a dopant concentration higher than the LDD implants. 
   
   
       14 . The integrated circuit of  claim 10 , further comprising a low voltage transistor comprising:
 a gate, and   a source and a drain in the substrate.   
   
   
       15 . The integrated circuit of  claim 10 , wherein the graded junctions are formed by annealing the integrated circuit. 
   
   
       16 . The integrated circuit of  claim 10 , wherein the gate of the high voltage transistor and the gate of the flash memory cell stacked above the floating gate are formed concurrently by etching a poly silicon layer. 
   
   
       17 . The integrated circuit of  claim 10 , wherein the integrated circuit has a nominal feature size less than approximately 130 nm. 
   
   
       18 . The integrated circuit of  claim 10 , wherein the integrated circuit is a programmable logic device. 
   
   
       19 . An integrated circuit comprising:
 a substrate;   a flash memory cell comprising:
 a floating gate, 
 a gate stacked above the floating gate, 
 oxidized sidewalls on the gates of the flash memory cell, and 
 a source and a drain in the substrate; and 
   a high voltage transistor comprising:
 a gate, 
 oxidized sidewalls on the gate of the high voltage transistor, 
 a channel m the substrate, and 
 means for providing a graded junction in relation to the channel. 
   
   
   
       20 . The integrated circuit of  claim 19 , wherein the high voltage transistor is adapted to sustain a programming voltage provided to the flash memory cell. 
   
   
       21 . The Integrated circuit of  claim 19 , wherein the high voltage transistor is adapted to sustain a programming voltage greater than approximately 9.5 volts provided to the flash memory cell. 
   
   
       22 . The integrated circuit of  claim 19 , wherein the high voltage transistor further comprises a source and a drain adjacent to the providing means, wherein the source and drain of the high voltage transistor have a dopant concentration higher than the providing means. 
   
   
       23 . The integrated circuit of  claim 19 , further comprising a low voltage transistor comprising:
 a gate, and   a source and a drain in the substrate,   
   
   
       24 . The integrated circuit of  claim 19 , wherein the graded junctions are formed by annealing the integrated circuit. 
   
   
       25 . The integrated circuit of  claim 19 , wherein the gate of the high voltage transistor and the gate of the flash memory cell stacked above the floating gate are formed concurrently by etching a poly silicon layer. 
   
   
       26 . The integrated circuit of  claim 19 , wherein the integrated circuit has a nominal feature size less than approximately 130 nm. 
   
   
       27 . The integrated circuit of  claim 19 , wherein the integrated circuit is a programmable logic device. 
   
   
       28 . An integrated circuit comprising:
 a substrate;   a high voltage transistor comprising:
 a gate, 
 oxidized sidewalls on the gate of the high voltage transistor, 
 a channel in the substrate, and 
 lightly doped drain (LDD) implants in the substrate and adjacent to the channel, wherein the LDD) implants form a graded junction in relation to the channel; and 
   a low voltage transistor comprising:
 a gate, and 
 a source and a drain in the substrate. 
   
   
   
       29 . The integrated circuit of  claim 28 , further comprising a flash memory cell comprising:
 a floating gate;   a gate stacked above the floating gate;   oxidized sidewalls on the gates of the flash memory cell; and   a source and a drain in the substrate.