Semiconductor Memory Device

Abstract

When an SRAM cell formed by six transistors is made finer and operated at a lower voltage, it does not operate stably. Because many transistors and control signals are required for stable operation, there is a problem that its component area is increased. An SRAM cell is formed by five transistors. The SRAM cell is formed by an inverter circuit (P 1 , N 1 ) using a storage node V 2 as an input and a storage node V 1 as an output, a load transistor P 2 connected between a power source VDD and the storage node V 2 with using the storage node V 1 as an input and the storage node V 2 as an output, an access transistor N 3 connected between a read bit line RBL and the storage node V 1 , and an access transistor N 4 connected between a write bit line WBL and the storage node V 2 . When the access transistor N 4 is controlled by a write word line WWL, the access transistor N 4 can be used as holding control means and writing means for the memory cell, making it possible to obtain a semiconductor device capable of operating at a high speed with a small number of elements.

1 . A semiconductor memory device having a memory cell, characterized in that: 
 said memory cell comprises: 
 an inverter circuit having a first storage node and a second storage node, said inverter circuit using said second storage node as an input and said first storage node as an output;  
 a load transistor connected between a power source and said second storage node, said load transistor using said first storage node as an input; and  
 holding control means connected to said second storage node.  
   
   
   
       2 . The semiconductor memory device as recited in  claim 1 , characterized in that said holding control means is formed by a first access transistor controlled by a write word line, and said first access transistor holds a level of said second storage node when the write word line has a first low level.  
   
   
       3 . The semiconductor memory device as recited in  claim 2 , characterized in that said first access transistor operates as an access transistor for writing during a writing operation.  
   
   
       4 . The semiconductor memory device as recited in  claim 2 , characterized in that said first access transistor has a threshold voltage lower than a threshold voltage of a second access transistor connected between a read bit line and said first storage node.  
   
   
       5 . The semiconductor memory device as recited in  claim 2 , characterized in that said first low level has a potential higher than a ground potential.  
   
   
       6 . The semiconductor memory device as recited in  claim 2 , characterized in that said first low level is supplied to a non-selected block, and a second low level signal lower than said first low level is supplied to a selected block, as a low level potential of said write word line in a writing cycle.  
   
   
       7 . The semiconductor memory device as recited in  claim 2 , characterized in that said first access transistor is connected to said second storage node and a write bit line, said memory cell further includes a second access transistor connected to said first storage node and a read bit line, a read word line is inputted to said second access transistor, data on said first storage node are read in a reading cycle by said second access transistor, and data are written into said memory cell via said second access transistor and said first access transistor in a writing cycle.  
   
   
       8 . The semiconductor memory device as recited in  claim 2 , characterized in that said first access transistor is connected to said second storage node and a ground potential, said memory cell further includes a second access transistor connected to said first storage node and a read bit line, a read word line is inputted to said second access transistor, data on said first storage node are read in a reading cycle by said second access transistor, and data from said second access transistor are written into said first storage node while said first access transistor resets said second storage node at a low level to perform a data writing operation in a writing cycle.  
   
   
       9 . A semiconductor memory device characterized by comprising: 
 an inverter circuit having a first storage node and a second storage node, said inverter circuit using said second storage node as an input and said first storage node as an output;    a load transistor connected between a power source and said second storage node, said load transistor using said first storage node as an input;    a first access transistor connected to said second storage node; and    a second access transistor connected between a read bit line and said first storage node,    wherein said first access transistor has a threshold value smaller than a threshold value of said second access transistor.    
   
   
       10 . A semiconductor device having a sense amplifier, characterized in that: 
 said sense amplifier comprises: 
 a read bit line and a write bit line for performing data transmission to a memory cell;  
 a data line for performing data transmission to an input-output circuit;  
 an inverter circuit using said read bit line as an input;  
 data reading means for transmitting an output of said inverter circuit to said data line;  
 first data writing means for transmitting data from said data line to said read bit line with using a write enable signal; and  
 second data writing means for transmitting inverse data of data from said data line to said write bit line with using an inverse write enable signal.  
   
   
   
       11 . The semiconductor memory device as recited in  claim 10 , characterized in that said sense amplifier further comprises pre-charging means for pre-charging said read bit line and level maintaining means using the output of said inverter circuit as an input for maintaining said read bit line at a high level when the output has a low level.  
   
   
       12 . The semiconductor memory device as recited in  claim 10 , characterized in that said data line is formed by a read data line connected to said reading means and a write data line connected to said first and second writing means.  
   
   
       13 . A semiconductor device having a sense amplifier, characterized in that: 
 said sense amplifier comprises: 
 a read bit line for performing data transmission to a memory cell;  
 a data line for performing data transmission to an input-output circuit;  
 an inverter circuit using said read bit line as an input;  
 reading means for transmitting an output of said inverter circuit to said data line; and  
 data writing means for transmitting data from said data line to said read bit line with using a write enable signal.  
   
   
   
       14 . The semiconductor memory device as recited in  claim 13 , characterized in that said sense amplifier further comprises pre-charging means for pre-charging said read bit line and level maintaining means using the output of said inverter circuit as an input for maintaining said read bit line at a high level when the output has a low level.  
   
   
       15 . The semiconductor memory device as recited in  claim 13 , characterized in that said data line is formed by a read data line connected to said reading means and a write data line connected to said first writing means.  
   
   
       16 . A semiconductor memory device characterized by comprising: 
 a read word line;    a write word line; and    a sub-word driver operable to select said read word line with using a main word signal and an inverse read block signal and select said write word line with using said main word signal and an inverse write block signal.    
   
   
       17 . The semiconductor memory device as recited in  claim 16 , characterized in that said sub-word driver has a first inverter circuit using said main word signal as an input and outputting said read word line, a first transistor having a drain, a source, and a gate connected to said read word line, a low potential power source, and said inverse write block signal, respectively, and a second transistor having a drain, a source, and a gate connected to a power source terminal of said first inverter circuit, a power source, and said inverse write block signal, respectively, and is operable to select said write word line.  
   
   
       18 . The semiconductor memory device as recited in  claim 17 , characterized in that said low potential power source is set to be a first low level potential for a non-selected block and a second low level potential lower than said first low level potential for a selected block during a writing cycle.  
   
   
       19 . The semiconductor memory device as recited in  claim 16 , characterized in that said inverse write block signal is generated from a write enable signal and said inverse read block signal.  
   
   
       20 . The semiconductor memory device as recited in  claim 16 , characterized in that said inverse write block signal is generated from a write enable signal, an inverse signal of a delay write enable signal generated by delaying said write enable signal, and said read block signal.  
   
   
       21 . A method of holding data in a semiconductor memory device having a memory cell, characterized in that said memory cell comprises an inverter circuit using a second storage node as an input and a first storage node as an output, a load transistor connected between a power source and said second storage node with using said first storage node as an input, and holding control means connected to said second storage node; said holding control means is connected between said second storage node and a write bit line and formed by a first access transistor using a write word line as a gate input; and data stored in said memory cell are held by setting an off-state current of said first access transistor to be larger than an off-state current of said load transistor and smaller than an on-state current of said load transistor when a first low level is supplied to said write word line.  
   
   
       22 . The holding method of a semiconductor memory device as recited in  claim 21 , characterized in that a second low level smaller than said first low level is supplied as a low level of said write word line in a selected block during a writing cycle.  
   
   
       23 . A method of reading from a semiconductor memory device having a memory cell, characterized in that said memory cell comprises an inverter circuit using a second storage node as an input and a first storage node as an output, a load transistor connected between a power source and said second storage node with using said first storage node as an input, and a second access transistor connected between said first storage node and a read bit line; and said second access transistor is brought into conduction by a read word line to read data stored on said first storage node.  
   
   
       24 . A method of writing to a semiconductor memory device having a memory cell, characterized in that said memory cell comprises an inverter circuit using a second storage node as an input and a first storage node as an output, a load transistor connected between a power source and said second storage node with using said first storage node as an input, a first access transistor connected between said second storage node and a write bit line, and a second access transistor connected between said first storage node and a read bit line; said first access transistor is brought into conduction by a write word line to write from said write bit line into said second storage node; and said second access transistor is brought into conduction by a read word line to write from said read bit line into said first storage node.  
   
   
       25 . A method of writing to a semiconductor memory device having a memory cell, characterized in that said memory cell comprises an inverter circuit using a second storage node as an input and a first storage node as an output, a load transistor connected between a power source and said second storage node with using said first storage node as an input, a first access transistor connected between said second storage node and a ground potential, and a second access transistor connected between said first storage node and a read bit line; said first access transistor is brought into conduction by a write word line of a one-shot pulse to reset said second storage node into a low level; and said second access transistor is brought into conduction by a read word line to write from said read bit line into said first storage node.  
   
   
       26 . The semiconductor memory device as recited in  claim 7 , characterized by further comprising a sense amplifier having an inverter circuit using said read bit line as an input, data reading means for transmitting an output of said inverter circuit to a data line, first data writing means for transmitting data from said data line to said read bit line with using a write enable signal, and second data writing means for transmitting inverse data of data from said data line to said read bit line with using an inverse write enable signal.  
   
   
       27 . The semiconductor memory device as recited in  claim 26 , characterized in that said sense amplifier further comprises pre-charging means for pre-charging said read bit line and level maintaining means using the output of said inverter circuit as an input for maintaining said read bit line at a high level when the output has a low level.  
   
   
       28 . The semiconductor memory device as recited in  claim 26 , characterized in that said data line is formed by a read data line connected to said reading means and a write data line connected to said first and second writing means.  
   
   
       29 . The semiconductor memory device as recited in  claim 8 , characterized by further comprising a sense amplifier having an inverter circuit using said read bit line as an input, reading means for transmitting an output of said inverter circuit to a data line, and data writing means for transmitting data from said data line to said read bit line with using a write enable signal.  
   
   
       30 . The semiconductor memory device as recited in  claim 29 , characterized in that said sense amplifier further comprises pre-charging means for pre-charging said read bit line and level maintaining means using the output of said inverter circuit as an input for maintaining said read bit line at a high level when the output has a low level.  
   
   
       31 . The semiconductor memory device as recited in  claim 29 , characterized in that said data line is formed by a read data line connected to said reading means and a write data line connected to said first and second writing means.  
   
   
       32 . The semiconductor memory device as recited in  claim 7 , characterized by further comprising a sub-word driver operable to generate said read word line with using a main word signal and an inverse read block signal and to generate said write word line with using said main word signal and an inverse write block signal.  
   
   
       33 . The semiconductor memory device as recited in  claim 32 , characterized in that said sub-word driver has a first inverter circuit using said main word signal as an input and outputting said read word line, a first transistor having a drain, a source, and a gate connected to said read word line, a low potential power source, and said inverse write block signal, respectively, and a second transistor having a drain, a source, and a gate connected to a power source terminal of said first inverter circuit, a power source, and said inverse write block signal, respectively, and is operable to select said write word line.  
   
   
       34 . The semiconductor memory device as recited in  claim 33 , characterized in that said low potential power source supplies, as a low level of said write word line, a first low level potential for a non-selected block and a second low level potential lower than said first low level potential for a selected block during a writing cycle.