High throughput AES architecture

Abstract

An advanced encryption system (AES) architecture includes a maximum parallel encryption module which implements one round of the AES algorithm in one clock cycle, and a maximum parallel key scheduling module which generates sub-keys in one clock cycle in parallel with the encryption module, thereby permitting feedback modes of operation to be used without adversely affecting AES throughput. A controller controls the operation of the encryption and key scheduling modules such that one round is completed per clock cycle. The controller is preferably part of a hierarchical distributed control scheme comprising communicating finite state machines (FSMs). The architecture also preferably includes asynchronous input and output buffers.

1 .- 24 . (canceled)  
     
     
         25 . An advanced encryption standard (AES) architecture which provides high throughput and low latency, comprising: 
 a parallel encryption circuit that receives a plurality of data bytes to be encrypted and implements one round of the AES algorithm in one clock cycle;    a parallel key scheduling circuit that generates sub-keys in one clock cycle in parallel with said parallel encryption module, said sub-keys provided to said parallel encryption module; and    a controller that controls the operation of said parallel encryption and key scheduling modules such that said AES architecture performs one round of the AES algorithm in one clock cycle;    wherein the parallel key scheduling circuit generates sub-keys and schedules operations in parallel with the maximum parallel encryption circuit, thereby permitting feedback used by the AES algorithm to increase parallelization of AES encryption.    
     
     
         26 . The AES architecture of  claim 25 , further comprising: 
 an asynchronous input buffer that receives data bytes to be encrypted, buffers a plurality of said data bytes in parallel, and provides parallel data bytes to said parallel encryption circuit; and    an asynchronous output buffer that receives an output of said parallel encryption circuit and outputs encrypted data bytes to an output bus.    
     
     
         27 . The AES architecture of  claim 26 , wherein said parallel encryption circuit comprises: 
 a substitution sub-circuit comprising substitution blocks which are replicated as needed to receive all of said parallel data bytes from said asynchronous input buffer simultaneously;    a shift row sub-circuit which receives the outputs of said substitution sub-circuit;    a mix column sub-circuit which receives the outputs of said shift row sub-circuit; and    a key addition sub-circuit that receives and combines the outputs of said mix column sub-circuit and said sub-keys from said parallel key scheduling circuit, and provides the results at an output, said output being the output of said parallel encryption circuit.    
     
     
         28 . The AES architecture of  claim 27 , wherein said parallel encryption and key scheduling circuits are implemented exclusively with combinatorial logic.  
     
     
         29 . The AES architecture of  claim 26 , wherein said controller is implemented with a hierarchical distributed control scheme comprising communicating finite state machines (FSMs), comprising: 
 a main FSM; and    local FSMs which are controlled by said main FSM, said local FSMs comprising: 
 a parallel encryption circuit FSM which controls said parallel encryption circuit;  
 a key scheduling circuit FSM which controls said key scheduling circuit;  
 an input buffer FSM which controls said asynchronous input buffer; and  
 an output buffer FSM which controls said asynchronous output buffer.  
   
     
     
         30 . The AES architecture of  claim 25 , wherein said controller is implemented with a hierarchical distributed control scheme comprising communicating finite state machines (FSMs).  
     
     
         31 . The AES architecture of  claim 25 , wherein said AES architecture implements a Rijndael algorithm with a data-blocks length of 128, 192 or 256 bits and a key-length of 128, 192 or 256 bits.  
     
     
         32 . The AES architecture of  claim 25 , wherein said AES architecture implements the AES standard with a data-block length of 128 bits and a key-length of 128, 192 or 256 bits.  
     
     
         33 . The AES architecture of  claim 25 , wherein said AES architecture implements an electronic code book (ECB) mode of operation.  
     
     
         34 . The AES architecture of  claim 25 , wherein said AES architecture implements a feedback mode of operation.  
     
     
         35 . The AES architecture of  claim 25 , comprising: 
 a parallel encryption circuit that receives the output of said asynchronous input buffer and implements one round of the AES algorithm in one clock cycle;    wherein said controller is a hierarchical distributed control scheme comprising communicating finite state machines (FSMs).    
     
     
         36 . The AES architecture of  claim 35 , wherein said parallel encryption circuit comprises: 
 a substitution sub-circuit comprising substitution blocks which are replicated as needed to receive all of said parallel data bytes from said asynchronous input buffer simultaneously;    a shift row sub-circuit which receives the outputs of said substitution sub-circuit;    a mix column sub-circuit which receives the 10 outputs of said shift row sub-circuit; and    a key addition sub-circuit that receives and combines the outputs of said mix column sub-circuit and said sub-keys from said parallel key scheduling circuit, and provides the results at an output, said output being the output of said parallel encryption circuit;    each of said parallel encryption module sub-circuits implemented exclusively with combinatorial logic.    
     
     
         37 . The AES architecture of  claim 35 , wherein said communicating FSMs comprise: 
 a main FSM; and    local FSMs which are controlled by said main FSM, said local FSMs comprising: 
 a parallel encryption circuit FSM which controls said parallel circuit module;  
 a key scheduling circuit FSM which controls said key scheduling circuit;  
 an input buffer FSM which controls said asynchronous input buffer; and  
 an output buffer FSM which controls said asynchronous output buffer.  
   
     
     
         38 . The AES architecture of  claim 35 , wherein said AES architecture implements a Rijndael algorithm with a data-blocks length of 128, 192 or 256 bits and a key-length of 128, 192 or 256 bits.  
     
     
         39 . The AES architecture of  claim 35 , wherein said AES architecture implements the AES standard with a data-block length of 128 bits and a key-length of 128, 192 or 256 bits.  
     
     
         40 . The AES architecture of  claim 35 , wherein said AES architecture implements the electronic code book (ECB) mode of operation.  
     
     
         41 . The AES architecture of  claim 35 , wherein said AES architecture implements a feedback mode of operation.  
     
     
         42 . The AES architecture of  claim 41 , wherein said AES architecture implements a Cipher Block Chaining (CBC) feedback mode of operation.  
     
     
         43 . The AES architecture of  claim 41 , wherein said AES architecture implements a Cipher Feedback (CFB) feedback mode of operation.  
     
     
         44 . The AES architecture of  claim 41 , wherein said AES architecture implements an Output Feedback (OFB) feedback mode of operation.