Semiconductor memory device

Abstract

A method of forming a circuit includes providing a substrate; providing an interconnect region positioned on the substrate; bonding a device structure to a surface of the interconnect region; and processing the device structure to form a first stack of layers on the interconnect region and a second stack of layers on the first stack. The width of the first stack is different than the width of the second stack.

1 . A method of forming a circuit, comprising: 
 providing a substrate;    providing an interconnect region positioned on the substrate;    bonding a device structure to a surface of the interconnect region; and    processing the device structure to form a first stack of layers and a second stack of layers on the first stack, the width of the first stack being different than the width of the second stack.    
     
     
         2 . The method of  claim 1 , wherein the step of processing the device structure includes providing at least one of the first and second stacks with tapered sidewalls.  
     
     
         3 . The method of  claim 1 , wherein each of the first and second stacks includes at least one pn junction, the current flow through the pn junction(s) flowing between the first and second stacks.  
     
     
         4 . The method of  claim 1 , further including providing a control terminal in communication with at least one of the stacks.  
     
     
         5 . The method of  claim 4 , wherein the stack and the control terminal operates as one of a vertically oriented transistor device and a vertically oriented thyristor device.  
     
     
         6 . The method of  claim 1 , wherein the substrate carries horizontally oriented electronic devices and the first and second stacks communicate with the horizontally oriented electronic devices through the interconnect region.  
     
     
         7 . The method of  claim 1 , further including providing first and second dielectric regions around the outer periphery of the first and second stacks, respectively.  
     
     
         8 . The method of  claim 7 , further including providing first and second control terminals around the outer periphery of the first and second dielectric regions, respectively, the conductance of the first and second stacks being adjustable in response to signals provided to corresponding first and second control terminals.  
     
     
         9 . The method of  claim 1 , further including choosing the width of the first stack to obtain a desired resistance thereof.  
     
     
         10 . A method of forming a circuit, comprising: 
 providing a substrate which carries an electronic circuit;    providing an interconnect region in communication with the electronic circuit;    bonding a device structure to the interconnect region; and    processing the device structure to form first and second stacks of layers, wherein one of the first and second stacks operates as a transistor and the other one operates as a negative differential resistance device.    
     
     
         11 . The method of  claim 10 , further including forming the first and second stacks so they have different widths.  
     
     
         12 . The method of  claim 10 , wherein the device structure is processed after the substrate is provided.  
     
     
         13 . The method of  claim 10 , wherein the device structure is processed after it is bonded to the interconnect region.  
     
     
         14 . The method of  claim 10 , further including forming the electronic circuit before processing the device structure.  
     
     
         15 . The method of  claim 10 , wherein the transistor is a vertically oriented transistor and the negative differential resistance device is a vertically oriented negative differential device.  
     
     
         16 . A method of forming a circuit, comprising: 
 providing a substrate;    forming electronic circuitry carried by the substrate, wherein the electronic circuitry includes horizontally oriented semiconductor devices;    forming an interconnect region connected to the electronic circuitry;    bonding a device structure so it is coupled to the interconnect region; and    processing the device structure to form a first stack of layers and a second stack of layers on the first stack, the width of the first stack being different than the width of the second stack.    
     
     
         17 . The method of  claim 16 , further including processing the first and second stacks so they operate as vertically oriented semiconductor devices.  
     
     
         18 . The method of  claim 16 , further including processing the first and second stacks so one operates as a transistor and the other operates as a thyristor.  
     
     
         19 . The method of  claim 18 , wherein the first and second stacks are processed after the device structure is bonded so it is coupled to the interconnect region.  
     
     
         20 . The method of  claim 18 , wherein the first and second stacks are processed after the electronic circuitry is formed.