Fault tolerant cell array architecture

Abstract

A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

1 . A fault tolerant data processing architecture comprising a network of cells containing memory, processors that can be organized into a fault-free array, wherein each cell comprises: 
 a global input;    optical direct output means;    a count register;    a negative of a cell address; and    the processing power to add a number from the global input to the count register and check a result for a register overflow.    
   
   
       2 . The architecture as claimed in  claim 1  wherein a type of the direct optical output means is selected from a group consisting of light emitting diodes, liquid crystal display, semi-conductor lasers, ultra-miniature cathode ray tubes, field emitter displays and porous silicon.  
   
   
       3 . In a fault tolerant data processing architecture a method for compressing and decompressing data for dynamic and static displays comprising 
 adding a number of cells controlled by an instruction to a counter register; and    determining a new value for a direct output means when the counter register overflows based on an opcode and a data portion of the instruction,    wherein the opcode portion of the instruction is chosen from a list comprising “this cell's output becomes” (COB), “next N cell's output becomes the data portion” (NCOB), “next N cell's output remains unchanged” (NCRU), and “reset” (RES).    
   
   
       4 . A fault tolerant data processing architecture comprising a network of cells containing memory, processors that can be organized into a fault-free array, wherein each cell comprises: 
 means for communicating with neighboring cells;    optical direct output means;    a count register;    a negative of a cell address; and    the processing power to add a number from the global input to the count register and check a result for a register overflow.    
   
   
       5 . In a fault tolerant data processing architecture a method for compressing and decompressing data for dynamic and static displays comprising 
 passing a reset opcode from a current cell to a next cell in a data stream;    receiving a “cell's output becomes” (COB) opcode with following data for an output value for output means of the current cell; and removing the COB opcode and following data from the data stream;    receiving a “next N cell's output becomes” (NCOB) opcode with following data for an output value for output means of next N cells; decrementing a cell control counter; if N is zero then the NCOB opcode and following data is removed from the data stream; and    receiving a “next N cell's output remains unchanged” (NCRU);    decrementing the cell control counter; if N is zero then the NCRU opcode and following data is removed from the data stream.    
   
   
       6 . A monolithic array of cells comprising: 
 a bus;    direct outputs connected to the bus;    at least a portion of the monolithic array of cells comprises the direct outputs for collectively forming a human-readable display upon using light; and    at least another portion of monolithic array of cells for using light not used by the direct outputs for another purpose.    
   
   
       7 . The monolithic array of cells as in  claim 6 , wherein the at least another portion of the monolithic array of cells forms a photovoltaic receptor cell for absorbing light not used by the direct outputs.  
   
   
       8 . The monolithic array of cells as in  claim 7 , wherein the direct outputs comprise reflective direct outputs for forming the human-readable display upon reflecting light.  
   
   
       9 . The monolithic array of cells as in  claim 7 , wherein said another purpose comprises powering said monolithic array of cells using the photovoltaic receptor cell.