Semiconductor integrated circuit device and internal power control system including the same

Abstract

One object of the present invention is to provide an LSI that can dynamically perform appropriate adjustment for a power voltage to be supplied to an internal circuit, not only at the time of the occurrence of the initial change of a performance due to a variation or variety factors through a manufacturing process, but also at the time of the occurrence of the time elapsed change. An LSI 13 includes a semiconductor substrate 14 , a ring oscillator 17 formed on the semiconductor substrate 14 and for outputting a monitoring clock signal MCLK having a frequency that depends on a manufacturing process, an internal circuit 16 formed on the semiconductor substrate 14 ; a frequency comparison circuit 18 for comparing the monitoring the clock signal MCLK with a reference clock signal RCLK having a predetermined frequency, and for outputting a differential signal DIF corresponding to the difference between the frequencies; and an internal power supply circuit 19 for supplying an internal power voltage IVDD to the internal circuit 16 , corresponding to the differential signal DIF that is outputted by the frequency comparison circuit 18 . Further provided is a design structure embodied in a machine readable medium used in a design process, where the design structure includes such LSI.

1 . A design structure embodied in a machine readable medium used in a design process, the design structure comprising: 
 a semiconductor integrated circuit device comprising:    a semiconductor substrate;    an oscillator formed on said semiconductor substrate, and for outputting a monitoring clock signal, said monitoring clock signal having a frequency that depends on a manufacturing process;    an internal circuit formed on said semiconductor substrate;    a frequency comparison circuit for comparing the monitoring clock signal outputted by said oscillator with a reference clock signal having a predetermined frequency, and for outputting a differential signal corresponding to the difference between the frequencies of the monitoring clock signal and the reference clock signal; and    an internal power supply circuit for supplying an internal power voltage to said internal circuit, corresponding to the differential signal outputted by said frequency comparison circuit.    
   
   
       2 . The design structure of  claim 1 , wherein said semiconductor integrated circuit device comprises a frequency comparison circuit, which includes: 
 a pulse thinning circuit for outputting a thinned-out clock signal by thinning out (n−2) pulses for every n pulses included in the reference clock signal, and for maintaining two pulses;    a frequency dividing circuit for frequency-dividing the monitoring clock signal to a 1/n frequency thereof, and for outputting a frequency-divided clock signal;    a differentiating circuit for differentiating the frequency-divided clock signal outputted by said frequency dividing circuit in synchronization with the reference clock signal, and for outputting a differentiated clock signal;    a pulse number comparison circuit for comparing the number of pulses of the thinned-out clock signal outputted by said pulse thinning circuit with the number of pulses of the differentiated clock signal outputted by said differentiating circuit, and for generating the differential signal in accordance with the obtained difference.    
   
   
       3 . The design structure of  claim 2 , wherein said semiconductor integrated circuit device comprises a pulse number comparison circuit, which includes: 
 a first counter for counting the number of pulses of the thinned-out clock signal;    a second counter for counting the number of pulses of the differentiated clock signal;    a subtracter for calculating a pulse number difference between the number of pulses obtained by said first counter and the number of pulses obtained by said second counter; and    a digital/analog converter for performing digital-analog conversion for the pulse number difference obtained by said subtracter to obtain the differential signal.    
   
   
       4 . The design structure of  claim 2 , wherein said semiconductor integrated circuit device comprises a pulse number comparison circuit, which includes: 
 a first LC filter for receiving the thinned-out clock signal;    a second LC filter for receiving the differentiated clock signal; and    a voltage comparator for comparing the output voltage of said first LC filter with the output voltage of said second LC filter, and for generating the differential signal in accordance with the difference between the output voltages.    
   
   
       5 . The design structure of  claim 2 , wherein semiconductor integrated circuit device comprises a differentiated circuit, which includes a first delay flip-flop circuit, a second delay flip-flop circuit and an exclusive OR circuit.  
   
   
       6 . The design structure of  claim 5 , wherein said semiconductor integrated circuit device comprises a first delay flip-flop circuit which latches the frequency-divided clock signal in synchronization with the reference clock signal.  
   
   
       7 . The design structure of  claim 1 , wherein said semiconductor integrated circuit device comprises a reference clock signal which is a system clock signal generated by a quartz oscillator or a phase locked loop circuit, and has a frequency which is substantially constant.  
   
   
       8 . The design structure of  claim 1 , which comprises a semiconductor integrated circuit device, wherein: when the frequency of the monitoring clock signal becomes higher than the frequency of the reference clock signal, the internal power voltage decreases; and when the frequency of the monitoring clock signal becomes lower than the frequency of the reference clock signal, the internal power voltage increases.  
   
   
       9 . A design structure embodied in a machine readable medium used in a design process, the design structure comprising: 
 an internal power control system comprising a semiconductor integrated circuit device;    said semiconductor integrated circuit device comprising:    a semiconductor substrate;    an oscillator formed on said semiconductor substrate, and for outputting a monitoring clock signal having a frequency that depends on a manufacturing process; and    an internal circuit formed on said semiconductor substrate; and    said internal power control system comprising:    a frequency comparison circuit for comparing the monitoring clock signal outputted by said oscillator with a reference clock signal having a predetermined frequency, and for outputting a differential signal corresponding to the difference between the frequencies of the monitoring clock signal and the reference clock signal; and    an internal power supply circuit for supplying an internal power voltage to said internal circuit, corresponding to the differential signal outputted by said frequency comparison circuit.    
   
   
       10 . The design structure of  claim 1 , wherein the design structure comprises a netlist, which describes the circuit.  
   
   
       11 . The design structure of  claim 1 , wherein the design structure resides on a GDS storage medium.  
   
   
       12 . The design structure of  claim 1 , wherein the design structure includes at least one item selected from the group consisting of test data files, characterization data, verification data, and design specifications.