Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance

Abstract

A semiconductor device. The semiconductor device includes a substrate includes: a substrate having a first gate stack on a surface of the substrate, wherein the first gate stack has a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate; an etch resistant first liner over the sidewalls of the first gate stack and not over the top surface of the first gate stack; a first outer spacer over the first liner, wherein the first liner is disposed between the first outer spacer and the sidewalls of the first gate stack, and wherein a portion of the first liner covers a first portion of the surface of the substrate; an insulative layer on a second portion of the surface of the substrate; and a conductive layer on the top surface of the first gate stack.

1 . A semiconductor device, comprising: 
 a substrate having a first gate stack on a surface of the substrate, said first gate stack having a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate;    an etch resistant first liner over the sidewalls of the first gate stack and not over the top surface of the first gate stack;    a first outer spacer over the first liner, wherein the first liner is disposed between the first outer spacer and the sidewalls of the first gate stack, and wherein a portion of the first liner covers a first portion of the surface of the substrate;    an insulative layer on a second portion of the surface of the substrate, wherein the second portion of the surface of the substrate surrounds the first gate stack, wherein the insulative layer does not cover the first gate stack, and wherein a third portion of the surface of the substrate is not covered by the insulative layer or the first liner; and    a conductive layer comprising a conductive material, wherein the conductive layer is on the top surface of the first gate stack and in direct mechanical contact with the top surface of the first gate stack.    
   
   
       2 . The semiconductor device of  claim 1 , further comprising a second gate stack on the surface of the substrate, said second gate stack having a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate.  
   
   
       3 . The semiconductor device of  claim 2 , further comprising: 
 an etch resistant second liner over the sidewalls of the second gate stack and not over the top surface of the second gate stack; and    a second outer spacer over the second liner, wherein the second liner is disposed between the second outer spacer and the sidewalls of the second gate stack, and wherein a portion of the second liner covers a fourth portion of the surface of the substrate.    
   
   
       4 . The semiconductor device of  claim 3 , wherein both the etch resistant first liner and the etch resistant second liner are in direct mechanical contact with the surface of the substrate.  
   
   
       5 . The semiconductor device of  claim 3 , wherein a maximum thickness of the second outer spacer in a direction parallel to the surface of the substrate exceeds a maximum thickness of the first outer spacer in the direction parallel to the surface of the substrate.  
   
   
       6 . The semiconductor device of  claim 3 , wherein the insulative layer covers both the second outer spacer and the top surface of the second gate stack.  
   
   
       7 . The semiconductor device of  claim 6 , wherein the insulative layer is in direct mechanical contact with both the second outer spacer and the top surface of the second gate stack.  
   
   
       8 . The semiconductor device of  claim 7 , further comprising: 
 a first inner spacer in direct mechanical contact with the sidewalls of the first gate stack, the first liner, the first outer spacer, and the substrate, wherein the first inner spacer is disposed between the first liner and the sidewalls of the first gate stack; and    a second inner spacer in direct mechanical contact with the sidewalls of the second gate stack, the second liner, the second outer spacer, and the substrate, wherein the second inner spacer is disposed between the second liner and the sidewalls of the second gate stack.    
   
   
       9 . The semiconductor device of  claim 8 , wherein a point on the first inner spacer farthest from the substrate is essentially a same distance from the substrate as is a distance from the substrate of a point on the conductive layer farthest from the substrate.  
   
   
       10 . The semiconductor device of  claim 8 , wherein a point on the second inner spacer farthest from the substrate is essentially a same distance from the substrate as is a distance from the substrate of a point on the second gate stack farthest from the substrate.  
   
   
       11 . The semiconductor device of  claim 10 , wherein the first gate stack comprises a transistor gate stack and the second gate stack comprises a resistor gate stack.  
   
   
       12 . The semiconductor device of  claim 11 , wherein the portion of the first liner that covers the first portion of the surface of the substrate extends to a designated location of transistor source and drain regions within the substrate.  
   
   
       13 . The semiconductor device of  claim 8 , 
 wherein the semiconductor device further comprises a first gate dielectric layer and a second gate dielectric layer;    wherein the first gate dielectric layer is disposed between the first gate stack and the surface of the substrate;    wherein the first gate dielectric layer is in direct mechanical contact with the first gate stack, the surface of the substrate, and the first inner spacer;    wherein the second gate dielectric layer is disposed between the second gate stack and the surface of the substrate; and    wherein the second gate dielectric layer is in direct mechanical contact with the second gate stack, the surface of the substrate, and the second inner spacer.    
   
   
       14 . The semiconductor device of  claim 1 , wherein the first gate stack consists of polysilicon.  
   
   
       15 . The semiconductor device of  claim 1 , wherein the semiconductor device further comprises a first gate dielectric layer disposed between the first gate stack and the surface of the substrate, and wherein the first gate dielectric layer is in direct mechanical contact with the first gate stack and the surface of the substrate.  
   
   
       16 . The semiconductor device of  claim 1 , wherein the conductive material comprises a silicide.  
   
   
       17 . The semiconductor device of  claim 1 , wherein the first liner comprises a material selected from the group consisting of Al 2 O 3 , HfO 2 , and Ta 2 O 3 .  
   
   
       18 . The semiconductor device of  claim 1 , wherein the first liner comprises SiC.  
   
   
       19 . The semiconductor device of  claim 1 , wherein the first liner comprises a material having a dielectric constant in a range of about 7-150.  
   
   
       20 . A semiconductor device, comprising: 
 a substrate having a first gate stack on a surface of the substrate, said first gate stack having a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate;    an etch resistant first liner over the sidewalls of the first gate stack and not over the top surface of the first gate stack;    a first outer spacer over the first liner, wherein the first liner is disposed between the first outer spacer and the sidewalls of the first gate stack, and wherein a portion of the first liner covers a first portion of the surface of the substrate;    an insulative layer on a second portion of the surface of the substrate, wherein the second portion of the surface of the substrate surrounds the first gate stack, wherein the insulative layer does not cover the first gate stack, and wherein a third portion of the surface of the substrate is not covered by the insulative layer or the first liner;    a conductive layer comprising a conductive material, wherein the conductive layer is on the top surface of the first gate stack and in direct mechanical contact with the top surface of the first gate stack    a second gate stack on the surface of the substrate, said second gate stack having a top surface parallel to the surface of the substrate and sidewalls perpendicular to the surface of the substrate;    an etch resistant second liner over the sidewalls of the second gate stack and not over the top surface of the second gate stack;    a second outer spacer over the second liner, wherein the second liner is disposed between the second outer spacer and the sidewalls of the second gate stack, and wherein a portion of the second liner covers a fourth portion of the surface of the substrate;    a first inner spacer in direct mechanical contact with the sidewalls of the first gate stack, wherein the first inner spacer is disposed between the first liner and the sidewalls of the first gate stack; and    a second inner spacer in direct mechanical contact with the sidewalls of the second gate stack, wherein the second inner spacer is disposed between the second liner and the sidewalls of the second gate stack, wherein the first inner spacer is in direct mechanical contact with the first liner, wherein the second inner spacer is in direct mechanical contact with the second liner, wherein the first gate stack comprises a transistor gate stack and the second gate stack comprises a resistor gate stack, wherein the portion of the first liner that covers the first portion of the surface of the substrate extends to a designated location of transistor source and drain regions within the substrate, and wherein the source and drain regions each comprise the conductive material.