Wirebond-less semiconductor package

Abstract

A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.

1 . A wirebond-less packaged semiconductor device comprising:
 a plurality of I/O contacts;   at least one semiconductor die, said semiconductor die having a bottom major surface and a top major surface, said top major surface having at least two electrically isolated electrodes; and   a conductive clip system disposed over said top major surface, said clip system comprising at least two electrically isolated sections coupling said electrodes to respective I/O contacts.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising an encapsulating layer, said encapsulating layer at least partially enclosing said die and clip system with said I/O contacts exposed therethrough. 
     
     
         3 . The device of  claim 2 , wherein a top surface of at least a portion of said conductive clip system is exposed through said encapsulating layer. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising a conductive leadframe disposed under said die, said conductive leadframe comprising said plurality of I/O contacts. 
     
     
         5 . The device of  claim 4 , wherein said bottom major surface of said semiconductor die is coupled to said leadframe with a first layer of conductive material, and wherein said top major surface of said semiconductor die is coupled to said clip system with a second layer of conductive material. 
     
     
         6 . The device of  claim 1 , wherein said semiconductor die comprises a power MOSFET device. 
     
     
         7 . The device of  claim 4 , wherein said top major surface of said die comprises a gate electrode and a source electrode and wherein said bottom major surface of said die comprises a drain electrode. 
     
     
         8 . The device of  claim 4 , wherein said top major surface of said die comprises a gate electrode and drain electrode and wherein said bottom major surface of said die comprises a source electrode. 
     
     
         9 . The device of  claim 1 , wherein said semiconductor die comprises a high-frequency power LDMOS device. 
     
     
         10 . A wirebond-less packaged semiconductor device comprising:
 a conductive leadframe defining a plurality of electrical I/O pads;   at least one semiconductor die, said semiconductor die having a bottom major surface with at least one electrode coupled to at least one of said electrical I/O pads, said at least one semiconductor die further comprising a top major surface having at least two electrically isolated electrodes;   a conductive clip system, said clip system comprising at least two electrically isolated portions coupling said at least two electrically isolated electrodes to respective electrical I/O pads of said leadframe; and   an encapsulating layer, said encapsulating layer at least partially enclosing said leadframe, die and clip system with said I/O pads exposed therethrough.   
     
     
         11 . The device of  claim 10 , wherein said bottom major surface of said semiconductor die is coupled to said leadframe with a first layer of conductive material, and wherein said top major surface of said semiconductor die is coupled to said clip system with a second layer of conductive material. 
     
     
         12 . The device of  claim 10 , wherein said semiconductor die comprises a power MOSFET device. 
     
     
         13 . The device of  claim 12 , wherein (i) said top major surface of said die comprises a gate electrode and a source electrode and wherein said bottom major surface of said die comprises a drain electrode, or (ii) said top major surface of said die comprises a gate electrode and a drain electrode and wherein said bottom major surface of said die comprises a source electrode. 
     
     
         14 . The device of  claim 10 , wherein said semiconductor die comprises a high frequency power LDMOS device. 
     
     
         15 . A method of forming a wirebond-less packaged semiconductor device comprising:
 providing a conductive leadframe defining a plurality of electrical I/O pads;   providing at least one semiconductor die, said die having a bottom major surface with at least one electrode and a top major surface having at least two electrically isolated electrodes;   coupling said at least one electrode from said bottom surface of said semiconductor die to at least one of said electrical I/O pads;   providing a conductive clip system, said clip system comprising at least two electrically isolated portions;   coupling said at least two electrically isolated electrodes from said top major surface to respective electrical I/O pads of said leadframe with said at least two electrically isolated portions of said clip system; and   at least partially encapsulating said leadframe, die and clip system within an encapsulating layer with said I/O pads exposed therethrough.   
     
     
         16 . The method of  claim 15 , wherein said conductive clip system is initially provided with said electrically isolated portions electrically connected together, the method further comprising the step of cutting a section of said clip system connecting said isolated portion, thereby electrically isolating said portions. 
     
     
         17 . The method of  claim 15 , wherein said cutting step occurs after said encapsulating step. 
     
     
         18 . The method of  claim 17 , wherein said cutting step comprises sawing through said section of said clip system. 
     
     
         19 . The method of  claim 16 , wherein said bottom major surface of said semiconductor die is coupled to said leadframe with a first layer of conductive material, and wherein said top major surface of said semiconductor die is coupled to said clip system with a second layer of conductive material. 
     
     
         20 . The method of  claim 16 , wherein said semiconductor die comprises a power MOSFET device. 
     
     
         21 . The method of  claim 20 , wherein (i) said top major surface of said die comprises a gate electrode and a source electrode and wherein said bottom major surface of said die comprises a drain electrode, or (ii) said top major surface of said die comprises a gate electrode and a drain electrode and wherein said bottom major surface of said die comprises a source electrode. 
     
     
         22 . The method of  claim 16 , wherein said semiconductor die comprises a power LDMOS device. 
     
     
         23 . The method of  claim 17 , wherein said cutting step comprising breaking off or snapping off a section of said clip system to isolate said portions. 
     
     
         24 . The method of  claim 23 , wherein said clip system comprises a pre-weakened region for permitting directed breaking or snapping off. 
     
     
         25 . The method of  claim 15 ,
 wherein said leadframe is provided in a matrix of individual leadframes,   wherein said conductive clip system is provided in a matrix of individual conductive clip systems, and   wherein said providing said at least one semiconductor die step comprises providing a plurality of semiconductor dies between said matrix of individual leadframes and said matrix of conductive clip systems, said method further comprising,   the method further comprising, after said encapsulating step, the step of cutting said matrixes to form individual packaged semiconductor devices.   
     
     
         26 . A wirebond-less packaged semiconductor device comprising:
 a conductive leadframe system defining a plurality of electrical I/O contacts;   a semiconductor die, said semiconductor die having a bottom major surface with a plurality of electrically isolated electrodes coupled to respective ones of said electrical I/O pads, said semiconductor die further comprising a top major surface having at least one electrode;   a conductive clip system disposed over said top surface of said die, said clip system comprising a main body portion coupled to said top surface electrode and comprising a downwardly depending leg portion coupling said main body portion to at one of said I/O contacts of said leadframe; and   an encapsulating layer, said encapsulating layer at least partially enclosing said leadframe system, die and clip system with said I/O contacts exposed therethrough.