US2008040575A1PendingUtilityA1

Parallel data processing apparatus

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Assignee: STUTTARD DAVEPriority: Apr 9, 1999Filed: Dec 22, 2006Published: Feb 14, 2008
Est. expiryApr 9, 2019(expired)· nominal 20-yr term from priority
Inventors:Dave StuttardDave WilliamsEamon O'DeaGordon FauldsJohn RhoadesKen CameronPhil AtkinPaul WinserRussell DavidRay McconnellTim DayTrey Greer
G06F 9/3888G06F 9/3887G06F 9/3851G06F 9/3004G06F 9/3885G06F 9/30101G06F 9/3838G06T 1/20G06F 9/30087G06F 15/8015G06F 15/8007G06F 9/3001
49
PatentIndex Score
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Claims

Abstract

A method of scheduling instruction streams in a SIMD (single instruction multiple data) array of processing elements in which the processing elements are arranged in a plurality of SIMD processing blocks, comprises determining which instruction stream has priority at a particular moment in time, and transferring that determined instruction stream to the SIMD array.

Claims

exact text as granted — not AI-modified
1 . A method of scheduling instruction streams in a SIMD (single instruction multiple data) array of processing elements in which the processing elements are arranged in a plurality of SIMD processing blocs, the method comprising determining which instruction stream has priority at a particular moment in time, and transferring that determined instruction stream to the SIMD array.  
     
     
         2 . A method as claimed in  claim 1 , % herein the determined instruction stream is transferred to all of the processing blocks in the array.  
     
     
         3 . A method as claimed in  claim 1 , wherein instructions streams are transferred to respective processing blocks of the array.  
     
     
         4 . A method as claimed in  claim 1 , comprising the step of 
 determining whether an instruction stream with higher priority than the currently active stream is ready to execute; and    if a higher priority instruction stream is ready to execute, activating the instruction stream having the higher priority.    
     
     
         6 . A method as claimed in  claim 1 , comprising the steps of 
 determining whether an active instruction stream has stalled; and    if a higher priority instruction stream is pending, activating the instruction stream having the higher priority.    
     
     
         7 . A method as claimed  claim 1 , wherein the instruction streams are synchronised with one another.  
     
     
         8 . A method as claimed in  claim 1 , wherein the instruction streams are synchronised with functional units external to the array of processing elements.  
     
     
         9 . A method as claimed in  claim 1 , comprising stalling an instruction stream when a functional unit external to the array of processing elements is unavailable.  
     
     
         10 . (canceled)  
     
     
         11 . A data processing apparatus comprising: 
 a SIMD (single instruction multiple data) array of processing elements, arranged in a plurality of SIMD processing blocks; and    a controller, for controlling the execution of a plurality of separate instruction streams, operable to determine which instruction stream has priority at a particular moment in time, and operable to transfer that instruction stream to the SIMD array.    
     
     
         12 . An apparatus as claimed in  claim 11 , wherein the controller is operable to transfer the determined instruction stream to all of the processing blocks in the array.  
     
     
         13 . An apparatus as claimed in  claim 11 , wherein the controller is operable to transfer instructions streams to respective processing blocks of the array.  
     
     
         14 . An apparatus as claimed in  claim 11 , wherein the controller is operable to: 
 determine whether an instruction stream with higher priority than the currently active stream is ready to execute; and    if a higher priority instruction stream is ready to execute, activate the instruction stream having the higher priority.    
     
     
         15 . An apparatus as claimed in  claim 11 , wherein the controller is operable to: 
 determine whether an active instruction stream his stalled; and    if a higher priority instruction stream is pending, actuate the instruction stream having the higher priority.    
     
     
         16 . An apparatus as claimed  claim 11 , wherein the instruction streams are synchronised with one another.  
     
     
         17 . An apparatus as claimed in  claim 11 , wherein the instruction streams are synchronised with functional units external to the array of processing elements.  
     
     
         18 . An apparatus as claimed in  claim 11 , provided on a single integrated circuit.  
     
     
         19 . An apparatus as claimed in  claim 11 , wherein the controller is operable to stall an instruction stream when a functional, unit external to the array of processing elements is unavailable.  
     
     
         20 . (canceled)  
     
     
         21 . A controller for controlling a data processor having a SIMD (single instruction multiple data) array of processing elements, arranged in a plurality of SIMD processing blocks, the controller being operable to control the execution of a plurality of separate instruction steams, and to determine which instruction stream has priority at a particular moment in time, and operable to transfer that instruction stream to the SIMD array.  
     
     
         22 . A controller as claimed in  claim 21 , operable to transfer the determined instruction stream to all of the processing blocks in the array.  
     
     
         23 . A controller as claimed in  claim 21 , operable to transfer instructions streams to respective processing blocks of the array.  
     
     
         24 . A controller as claimed in  claim 21 , operable to: 
 determine whether an instruction stream with higher priority than the currently active stream is ready to execute; and    if a higher priority instruction stream is ready to execute, activate the instruction stream having the higher priority.    
     
     
         25 . A controller as claimed in  claim 21 , operable to: 
 determine whether an active instruction stream has stalled; and    if a higher priority instruction stream is pending, activate the instruction stream having the higher priority.    
     
     
         26 . (canceled)  
     
     
         27 . A controller as claimed in  claim 21 , operable to synchronise the instruction streams with functional units external to the array of processing elements.  
     
     
         28 . A controller as claimed in  claim 21 , operable to stall an instruction stream when a functional unit external to the array of processing elements is unavailable.  
     
     
         29 . A controller as claimed in  claim 21 , operable to stall an instruction stream when a functional unit external to the array of processing elements is unavailable, and to restart a stalled instruction stream when the functional unit is available.

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