Vertical nitride semiconductor light emitting diode and method of manufacturing the same

Abstract

A vertical nitride-based semiconductor LED comprises a structure support layer; a p-electrode formed on the structure support layer; a p-type nitride semiconductor layer formed on the p-electrode; an active layer formed on the p-type nitride semiconductor layer; an n-type nitride semiconductor layer formed on the active layer; an n-electrode formed on a portion of the n-type nitride semiconductor layer; and a buffer layer formed on a region of the n-type nitride semiconductor layer on which the n-electrode is not formed, the buffer layer having irregularities formed thereon. The surface of the n-type nitride semiconductor layer coming in contact with the n-electrode is flat.

1 . A vertical nitride-based semiconductor light emitting diode (LED) comprising:
 a structure support layer;   a p-electrode formed on the structure support layer;   a p-type nitride semiconductor layer formed on the p-electrode;   an active layer formed on the p-type nitride semiconductor layer;   an n-type nitride semiconductor layer formed on the active layer;   an n-electrode formed on a portion of the n-type nitride semiconductor layer; and   a buffer layer formed on a region of the n-type nitride semiconductor layer on which the n-electrode is not formed, the buffer layer having irregularities formed thereon;   wherein the surface of the n-type nitride semiconductor layer coming in contact with the n-electrode is flat.   
   
   
       2 . A method of manufacturing a vertical nitride-based semiconductor LED comprising:
 sequentially forming a buffer layer, an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer on a substrate;   forming a p-electrode on the p-type nitride semiconductor layer;   forming a structure support layer on the p-electrode;   removing the substrate through an LLO(Laser Lift-Off) process;   selectively etching a portion of the buffer layer, on which the substrate is removed, so as to flatly expose a portion of the n-type nitride semiconductor layer;   forming an n-electrode on the flatly-exposed n-type nitride semiconductor layer; and   forming irregularities on the surface of the buffer layer which is not etched.   
   
   
       3 . The method according to  claim 2 , wherein in the etching of the buffer layer, a dry-etching process is used. 
   
   
       4 . A method of manufacturing a vertical nitride-based semiconductor LED comprising:
 sequentially forming a buffer layer, an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer on a substrate;   forming a p-electrode on the p-type nitride semiconductor layer;   forming a structure support layer on the p-electrode;   removing the substrate through an LLO(Laser Lift-Off) process;   selectively etching a portion of the buffer layer, on which the substrate is removed, so as to flatly expose a portion of the n-type nitride semiconductor layer;   forming irregularities on the surface of the buffer layer which is not etched; and   forming an n-electrode on the flatly-exposed n-type nitride semiconductor layer.   
   
   
       5 . The method according to  claim 4 ,
 wherein in the etching of the buffer layer, a dry-etching process is used.   
   
   
       6 . A method of manufacturing a vertical nitride-based semiconductor LED comprising:
 sequentially forming a buffer layer, an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer on a substrate;   forming a p-electrode on the p-type nitride semiconductor layer;   forming a structure support layer on the p-electrode;   removing the substrate through an LLO process;   forming irregularities on the entire surface of the buffer layer where the substrate is removed;   selectively etching a portion of the buffer layer, on which the irregularities are formed, so as to flatly expose a portion of the n-type nitride semiconductor layer; and   forming an n-electrode on the flatly-exposed n-type nitride semiconductor layer.   
   
   
       7 . The method according to  claim 6 ,
 wherein in the etching of the buffer layer, a dry-etching process is used.