Pixel clock generation device causing state transition of pixel clock according to detected state transition and phase data indicating phase shift amount

Abstract

A transition detection circuit detects a transition of a state of a pixel clock, and outputs a detection signal according to a timing of the detected state transition. A control signal generation circuit generates a control signal according to the detection signal and phase data indicating a transition timing of the pixel clock. A pixel clock control circuit causes the state of the pixel clock to transit according to the control signal.

1 . A pixel clock generation device comprising: 
 a high-frequency clock generation circuit generating a high-frequency clock;    a transition detection circuit detecting a transition of a state of a pixel clock, and outputting a detection signal according to a timing of the detected transition;    a control signal generation circuit generating a control signal according to said detection signal and phase data indicating a transition timing of said pixel clock; and    a pixel clock control circuit causing the state of said pixel clock to transit according to said control signal, wherein said pixel clock control circuit includes a JK-FF.    
   
   
       2 . A pixel clock generation device comprising: 
 a high-frequency clock generation circuit generating a high-frequency clock;    a transition detection circuit detecting a transition of a state of a pixel clock, and outputting a detection signal according to a timing of the detected transition;    a control signal generation circuit generating a control signal according to said detection signal and phase data indicating a transition timing of said pixel clock; and    a pixel clock control circuit causing the state of said pixel clock to transit according to said control signal, wherein said pixel clock control circuit includes a synchronously set/reset D-FF.    
   
   
       3 . A pixel clock generation device comprising: 
 a high-frequency clock generation part generating a high-frequency clock;    a clock generation part generating a plurality of clocks having different phases and/or periods according to phase data indicating a phase shift amount of a pixel clock, a status signal indicating a state of said pixel clock, and said high-frequency clock; and    a clock selecting part selecting either of said clocks according to said phase data, wherein said clock generation part includes,    a control data generation part generating a plurality of control data for controlling the phases and/or periods of said clocks according to said phase data and said status signal;    a transition detection part detecting transitions of states of said clocks, respectively, so as to generate detection signals;    a control signal generation part generating control signals indicating timings for controlling the phases and/or periods of said clocks, respectively, according to said detection signals and said control data; and    a state transition part causing the states of said clocks to transit according to said control signals, respectively, wherein said state transition part includes a JK-FF.    
   
   
       4 . A pixel clock generation device comprising: 
 a high-frequency clock generation part generating a high-frequency clock;    a clock generation part generating a plurality of clocks having different phases and/or periods according to phase data indicating a phase shift amount of a pixel clock, a status signal indicating a state of said pixel clock, and said high-frequency clock; and    a clock selecting part selecting either of said clocks according to said phase data, wherein said clock generation part includes,    a control data generation part generating a plurality of control data for controlling the phases and/or periods of said clocks according to said phase data and said status signal;    a transition detection part detecting transitions of states of said clocks, respectively, so as to generate detection signals;    a control signal generation part generating control signals indicating timings for controlling the phases and/or periods of said clocks, respectively, according to said detection signals and said control data; and    a state transition part causing the states of said clocks to transit according to said control signals, respectively, wherein said state transition part includes a synchronously set/reset D-FF.