Thin film transistor array panel for a display device and a method of manufacturing the same

Abstract

A method of manufacturing a thin film transistor array panel includes forming gate lines including gate electrodes on an insulation substrate; forming a gate insulating layer, semiconductor layer, and etch stop layer on the gate lines; etching and patterning the etch stop and semiconductor layers at the same time using photolithography; ashing and partially removing a photoresist film pattern used in the patterning of the etch stop and semiconductor layers; etching the etch stop layer exposed by removed portions of the photoresist film pattern to form etch stop members; depositing ohmic contact and data metal layers onto the etch stop members, etching the ohmic contact and data metal layers at the same time using photolithography to form data lines having source and drain electrodes, and ohmic contact members below the source and drain electrodes; forming a passivation layer on the data lines and drain electrodes; and forming pixel electrodes on the passivation layer.

1 . A thin film transistor array panel comprising:
 an insulation substrate;   gate lines formed on the insulation substrate and having gate electrodes;   a gate insulating layer formed on the gate lines;   semiconductors formed on the gate insulating layer;   etch stop members formed on portions of the semiconductors;   ohmic contact members formed on the etch stop members and partially contacting the semiconductors;   a data wire layer formed on the ohmic contact members and having substantially the same planar pattern as that of the ohmic contact members;   a passivation layer formed on the data wire layer and having contact holes; and   pixel electrodes formed on the passivation layer and connected to portions of the data wire layer through the contact holes.   
   
   
       2 . The thin film transistor array panel of  claim 1 , wherein the data wire layer comprises:
 data lines that have source electrodes and intersect the gate lines;   drain electrodes that are disposed on the gate electrodes and face the source electrodes; and   storage capacitor conductors that overlap the gate lines.   
   
   
       3 . The thin film transistor array panel of  claim 2 , wherein each of the semiconductors comprises a linear portion that is formed below a corresponding data line and a protruding portion that extends from the linear portion over a corresponding source electrode and drain electrode. 
   
   
       4 . The thin film transistor array panel of  claim 3 , wherein each of the etch stop members comprises a protruding portion that is formed on the protruding portion of a corresponding semiconductor to cover the corresponding semiconductor located between the corresponding source electrode and drain electrode and a linear portion that is formed on the linear portion of the corresponding semiconductor. 
   
   
       5 . The thin film transistor array panel of  claim 4 , wherein the linear portion of the etch stop members is located within an area defined by sides of the linear portion of the corresponding semiconductor. 
   
   
       6 . The thin film transistor array panel of  claim 4 , wherein the protruding portion of the etch stop members is located within an area defined by sides of the protruding portion of the corresponding semiconductor. 
   
   
       7 . The thin film transistor array panel of  claim 1 , wherein each of the semiconductors is formed of amorphous silicon, and each of the etch stop members is formed of silicon nitride. 
   
   
       8 . A method of manufacturing a thin film transistor array panel, comprising:
 forming gate lines including gate electrodes on an insulation substrate;   forming a gate insulating layer, a semiconductor layer, and an etch stop layer on the gate lines;   etching and patterning the etch stop layer and the semiconductor layer at the same time using photolithography;   ashing and partially removing a photoresist film pattern used in the etching and patterning of the etch stop layer and the semiconductor layer;   etching the etch stop layer exposed by removed portions of the photoresist film pattern to form etch stop members;   depositing an ohmic contact layer and a data metal layer onto the etch stop members;   etching the ohmic contact layer and the data metal layer at the same time using photolithography to form data lines having source electrodes, drain electrodes facing the source electrodes, and ohmic contact members below the source electrodes and the drain electrodes;   forming a passivation layer on the data lines and the drain electrodes; and   forming pixel electrodes on the passivation layer.   
   
   
       9 . The method of  claim 8 , wherein each of the ohmic contact members has substantially the same planar pattern as that of a data line and drain electrode formed thereon. 
   
   
       10 . The method of  claim 8 , further comprising:
 connecting the pixel electrodes to the drain electrodes.   
   
   
       11 . The method of  claim 8 , wherein the gate insulating layer, semiconductor layer, and etch stop layer are sequentially formed on the gate lines. 
   
   
       12 . A thin film transistor array panel comprising:
 an insulation substrate;   gate lines that are formed on the insulation substrate and that have first gate electrodes;   second gate electrodes and storage electrodes that are formed on the insulation substrate;   a gate insulating layer that is formed on the gate lines, the second gate electrodes, and the storage electrodes;   first and second semiconductors that are formed on the gate insulating layer;   first and second etch stop members that are formed on portions of the first and second semiconductors, respectively;   ohmic contact members that are formed on the first and second etch stop members and that partially contact the first and second semiconductors;   a data wire layer that is formed on the ohmic contact members and that has substantially the same planar pattern as that of the ohmic contact members;   a passivation layer that is formed on the data wire layer and that has a plurality of contact holes; and   pixel electrodes that are formed on the passivation layer and that are connected to portions of the data wire layer through the contact holes.   
   
   
       13 . The thin film transistor array panel of  claim 12 , wherein the data wire layer comprises:
 data lines that have first source electrodes and intersect the gate lines;   first drain electrodes that are disposed on the first gate electrodes and face the first source electrodes;   power lines that have second source electrodes and intersect the gate lines; and   second drain electrodes that are disposed on the second gate electrodes and face the second source electrodes,   wherein the thin film transistor array panel further comprises connecting members that electrically connect the first drain electrodes and the second gate electrodes to each other.   
   
   
       14 . The thin film transistor array panel of  claim 13 , wherein each of the first semiconductors has a linear portion that is formed below a corresponding data line, and a first channel portion that extends from the linear portion over a corresponding first source elect rode and first drain electrode,
 each of the second semiconductors has a storage electrode portion that overlaps a corresponding storage electrode, and a second channel portion that extends over a corresponding second source electrode and second drain electrode,   each of the first etch stop members covers the first semiconductor between the corresponding first source electrode and first drain electrode, and   each of the second etch stop members covers the second semiconductor between the corresponding second source electrode and second drain electrode.   
   
   
       15 . The thin film transistor array panel of  claim 14 , wherein the first and second semiconductors are formed of amorphous silicon, and the first and second etch stop members are formed of silicon nitride. 
   
   
       16 . The thin film transistor array panel of  claim 14 , further comprising:
 partition walls that are formed on the pixel electrodes;   a light emission layer that fills frames defined by the partition walls; and   a common electrode that is formed on the light emission layer.   
   
   
       17 . A method of manufacturing a thin film, transistor array panel, comprising:
 forming gate lines having first gate electrodes, second gate electrodes, and storage electrodes on an insulation substrate;   forming a gate insulating layer, a semiconductor layer, and an etch stop layer on the gate lines, the second gate electrodes, and the storage electrodes;   etching and patterning the etch stop layer and the semiconductor layer at the same time using photolithography;   ashing and partially removing a photoresist film pattern used in the etching and patterning of the etch stop layer and the semiconductor layer;   etching the etch stop layer exposed by removed portions of the photoresist film pattern to form first and second etch stop members;   depositing an ohmic contact layer and a data metal layer onto the first and second etch stop members;   etching the ohmic contact layer and data metal layer at the same time using photolithography to form data lines having first source electrodes, drain electrodes facing the first source electrodes, power lines having second source electrodes, second drain electrodes facing the second source electrodes, and ohmic contact members below the first and second drain electrodes;   forming a passivation layer on the data lines, the first drain electrodes, the power lines, and the second drain electrodes; and   forming on the passivation layer pixel electrodes that are connected to the second drain electrodes and connecting members that electrically connect the first drain electrodes and second gate electrodes to each other.   
   
   
       18 . The method of  claim 17 , wherein each of the ohmic contact members has substantially the same planar pattern as that of a data line, first drain electrode, power line, and second drain electrode formed thereon. 
   
   
       19 . The method of  claim 17 , further comprising:
 forming partition walls on the pixel electrodes;   forming an organic fight emission layer that fills frames defined by the partition walls; and   forming a common electrode on the organic light emission layer.   
   
   
       20 . The method of  claim 17 , wherein the gate insulating layer, semiconductor layer, and etch stop layer are sequentially formed on the gate lines, the second gate electrodes, and the storage electrodes.