US2008048327A1PendingUtilityA1

Electronic circuit with embedded memory

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Assignee: LEE SANG-YUNPriority: Jun 21, 2004Filed: Oct 17, 2007Published: Feb 28, 2008
Est. expiryJun 21, 2024(expired)· nominal 20-yr term from priority
Inventors:Sang-Yun Lee
H10D 88/00H10D 86/00H10D 30/6728G11C 5/02G11C 5/04H10B 10/18H10B 10/00H10B 12/01H10B 69/00H10B 43/30
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Claims

Abstract

Circuitry includes first and second circuits spaced apart by an interconnect region. The interconnect region includes a first interconnect and the second circuit includes a stack of semiconductor layers. The first interconnect extends between the first and second circuits to provide communication therebetween. The second circuit operates as a memory circuit.

Claims

exact text as granted — not AI-modified
1 . Circuitry comprising: 
 a first circuit;    an interconnect region;    a first interconnect included in the interconnect region; and    a second circuit spaced apart from the first circuit by the interconnect region, the second circuit including a stack of semiconductor layers; and    wherein the first interconnect extends between the first and second circuits to provide communication therebetween.    
     
     
         2 . The circuitry of  claim 1 , wherein the stack of semiconductor layers operates as a vertically oriented memory device.  
     
     
         3 . The circuitry of  claim 1 , further including a third circuit positioned near the first circuit so that the second circuit is spaced apart from the first and third circuits by the interconnect region.  
     
     
         4 . The circuitry of  claim 3 , further including a second interconnect extending through the interconnect region to provide communication between the first and third circuits.  
     
     
         5 . The circuitry of  claim 1 , wherein the stack of semiconductor layers operates as a vertically oriented negative differential resistance static random access memory device.  
     
     
         6 . The circuitry of  claim 1 , wherein at least a portion of the second circuit includes a crystalline semiconductor material region.  
     
     
         7 . Circuitry comprising: 
 first and second circuits, the second circuit including a vertically oriented semiconductor device which includes a stack of semiconductor layers; and    an interconnect region which includes a first interconnect, the interconnect region extending between the first and second circuits;    wherein the first and second circuits are in communication with each other through the first interconnect.    
     
     
         8 . The circuitry of  claim 7 , further including a third circuit positioned near the first circuit so that the second circuit is spaced apart from the first and third circuits by the interconnect region.  
     
     
         9 . The circuitry of  claim 8 , wherein the interconnect region includes a second interconnect extending between the second and third circuits.  
     
     
         10 . The circuitry of  claim 8 , further including a third interconnect which extends between the first and third circuits.  
     
     
         11 . The circuitry of  claim 7 , wherein the vertically oriented semiconductor device operates as a memory device.  
     
     
         12 . The circuitry of  claim 7 , wherein the vertically oriented semiconductor device operates as a negative differential resistance static random access memory device.  
     
     
         13 . The circuitry of  claim 7 , wherein at least a portion of the third circuit includes a crystalline semiconductor material region.  
     
     
         14 . The circuitry of  claim 7 , wherein the stack of semiconductor layers is bonded to the interconnect region.  
     
     
         15 . Circuitry comprising: 
 an interconnect region which includes a first interconnect; and    first and second circuits in communication with each other through the first interconnect, the second circuit including a stack of semiconductor layers;    wherein the second circuit is bonded to the interconnect region.    
     
     
         16 . The circuitry of  claim 15 , wherein the interconnect region extends between the first and second circuits.  
     
     
         17 . The circuitry of  claim 16 , further including a third circuit, wherein the interconnect region extends between the second and third circuits.  
     
     
         18 . The circuitry of  claim 17 , wherein first and third circuits include laterally oriented semiconductor devices.  
     
     
         19 . The circuitry of  claim 15 , wherein second circuit does not include laterally oriented semiconductor devices.  
     
     
         20 . The circuitry of  claim 15 , wherein second circuit includes a vertically oriented semiconductor device.

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