Method and apparatus for detection and prevention of bulk cmos latchup

Abstract

A method and apparatus are provided for detection and prevention of bulk complementary metal oxide semiconductor (CMOS) latchup. A separate power distribution is provided for coupling a positive voltage supply rail to the N well and a ground voltage supply rail to the P well of the CMOS circuit. At least one sensor monitors current flow in a bias voltage applied to at least one of an N well and a P well of the CMOS circuitry. A latchup event is detected responsive to a predefined increase in the monitored current flow. A switch temporarily interrupts the connection of at least one of the N well and the P well to the respective voltage supply rail when the latchup event is detected.

1 - 6 . (canceled)  
   
   
       7 . Apparatus for detection and prevention of bulk CMOS latchup comprising: 
 a sensor for monitoring current flow in a bias voltage applied to an N well of the CMOS circuitry; a latchup event being detected responsive to a predefined increase in the monitored current flow;    a separate power distribution for coupling a positive voltage supply rail to the N well of the CMOS circuitry and a ground voltage supply rail to the P well; and    a switch for temporarily interrupting a connection of the N well and the CMOS circuitry positive voltage supply rail to the positive voltage supply rail responsive to the latchup event being detected.    
   
   
       8 . Apparatus for detection and prevention of bulk CMOS latchup as recited in  claim 7  wherein said sensor includes a sensor contact connected to the N well, a sensor resistor coupled between said sensor contract and a positive voltage supply rail.  
   
   
       9 . Apparatus for detection and prevention of bulk CMOS latchup as recited in  claim 8  further includes a comparator coupled to said sensor resistor; said comparator proving a control signal to said switch and said control signal provides an output control signal to a separate monitor logic responsive to the latchup event being detected.  
   
   
       10 . Apparatus for detection and prevention of bulk CMOS latchup as recited in  claim 7  further includes a sensor for monitoring current flow to the P well of the CMOS circuitry; a latchup event being detected responsive to a predefined increase in the monitored current flow.  
   
   
       11 . Apparatus for detection and prevention of bulk CMOS latchup as recited in  claim 7  further includes a switch for temporarily interrupting a connection of the P well and the CMOS circuitry ground voltage supply rail to the ground voltage supply rail responsive to the latchup event being detected.  
   
   
       12 . Apparatus for detection and prevention of bulk CMOS latchup as recited in  claim 7  wherein said at least one switch includes a field effect transistor.  
   
   
       13 . A method for detecting and preventing latchup in a bulk CMOS circuit comprising the steps of: 
 providing a separate power distribution for coupling a positive voltage supply rail to the N well of the CMOS circuit and a ground voltage supply rail to the P well of the CMOS circuit;    monitoring current flow in a bias voltage applied to the N well of the CMOS circuit;    detecting a latchup event responsive to a predefined increase in the monitored current flow;    providing a switch coupled between the positive voltage supply rail and the N well and the CMOS circuit;    applying a switch control signal to said switch for temporarily interrupting a connection of the N well and the CMOS circuit voltage supply rail to the voltage supply rail responsive to the latchup event being detected.    
   
   
       14 . A method for detecting and preventing latchup in a bulk CMOS circuit as recited in  claim 13  wherein monitoring current flow in a bias voltage applied to the N well of the CMOS circuit includes providing a sensor contact connected to the N well of the CMOS circuit; and providing a sensor resistor coupled between said sensor contract and the positive voltage supply rail; and providing a comparator coupled to said sensor resistor; said comparator providing said switch control signal to said switch and said control signal providing an output control signal to a separate monitor logic responsive to the latchup event being detected.  
   
   
       15 . A method for detecting and preventing latchup in a bulk CMOS circuit as recited in  claim 13  further includes monitoring current flow to the P well of the CMOS circuitry and providing a switch coupled between the ground voltage supply rail and the P well and the CMOS circuitry.