Method And Device For Operand Processing In A Processing Unit

Abstract

A method and a device for operand processing in a processing unit having at least two execution units, which are able to be operated at a predefinable clock cycle. The execution units are controlled by control signals for the processing of the operands and a switch is possible between a first operating mode and a second operating mode. In the first operating mode, both execution units are supplied with the same operands, and in the second operating mode different operands are supplied to both execution units, and both execution units are controlled by the same control signals for the processing of the operands in the first operating mode, and both execution units are controlled by different control signals for the processing of the operands in the second operating mode.

1 - 24 . (canceled) 
   
   
       25 . A method for processing operands in a processing unit having at least two execution units, comprising:
 operating the executing units at a predefinable clock cycle;   triggering the execution units by control signals for a processing of the operands;   switching between a first operating mode and a second operating mode;   in the first operating mode, supplying the execution units with the same operands; and   in the second operating mode, supplying the execution units with different operands,
 wherein:
 the execution units are triggered by the same control signals for the processing of the operands in the first operating mode, and 
 the execution units are controlled by different control signals for the processing of the operands in the second operating mode. 
 
   
   
   
       26 . The method as recited in  claim 25 , further comprising:
 supplying the operands to the execution units as a function of the clock cycle for operand processing of the execution units in the form of a full cycle; and   in the second operating mode, supplying the operands at a second clock cycle for the processing of the operands, the second cycle being faster than the full cycle, one of the execution units thereby receiving operands after a time offset passes from a time at which another of the execution units receives operands in a same clock cycle.   
   
   
       27 . The method as recited in  claim 26 , wherein in the first operating mode the operands are supplied at the clock cycle of the execution units, as full cycle. 
   
   
       28 . The method as recited in  claim 26 , wherein, compared to the full cycle, the faster second clock cycle is designed as half cycle and is twice as fast and the time offset is equal to half of the full cycle. 
   
   
       29 . The method as recited in  claim 25 , wherein the execution units process the operands in synchrony in the first operating mode and the second operating mode. 
   
   
       30 . The method as recited in  claim 25 , further comprising:
 processing the operands in synchrony in the first operating mode; and   processing the operands in asynchrony in the second operating mode.   
   
   
       31 . The method as recited in  claim 25 , further comprising:
 comparing one of the operands and data derived from the operands for agreement; and   detecting an error in case of a deviation.   
   
   
       32 . The method as recited in  claim 25 , further comprising:
 comparing one of states and results produced in the processing of the operands for agreement; and   detecting an error in a deviation, the comparison being implementable as a function of the individual operating mode.   
   
   
       33 . The method as recited in  claim 32 , further comprising:
 releasing the one of the states and the results by a release signal as a function of the operating mode and the comparison.   
   
   
       34 . The method as recited in  claim 32 , further comprising:
 releasing the one of the states and results by a release signal one of simultaneously and successively as a function of the operating mode.   
   
   
       35 . A device for operand processing in a processing unit having at least two execution units, comprising:
 an arrangement for operating the execution units at a predefinable clock cycle; and   a control unit for triggering the execution units by control signals for a processing of the operands and for switching between a first operating mode and a second operating mode,   wherein:
 the control unit is connected to the execution units and additional feed units, 
 the control unit cooperates with the feed units in such a way that both execution units are supplied with the same operands in the first operating mode and both execution units are supplied with different operands in the second operating mode, and 
 the control unit being designed such that both execution units are triggered by identical control signals for the processing of the operands in the first operating mode and both execution units are triggered by different control signals for the processing of the operands in the second operating mode. 
   
   
   
       36 . The device as recited in  claim 35 , wherein the control unit and the feed units are designed such that in the first operating mode the operands are supplied to the execution units as a function of the clock cycle of the execution units, as full cycle, and in the second operating mode the operands are supplied for processing at a second clock cycle, which is faster than the full cycle, one of the execution units thereby receiving operands after a time offset passes from a time at which another of the execution units receives operands in a same clock cycle. 
   
   
       37 . The device as recited in  claim 35 , wherein the execution units are embodied as at least one of arithmetic logic units, floating point units, processors, and a coprocessor. 
   
   
       38 . The device as recited in  claim 35 , wherein the feed units and the execution units are designed such that in the first operating mode they operate in synchrony using an identical clock cycle. 
   
   
       39 . The device as recited in  claim 35 , wherein the feed units as register system are designed such that at least one operand register is provided and at least one buffer register is provided between operand register and each execution unit. 
   
   
       40 . The device as recited in  claim 35 , wherein the feed units and the execution units are designed such that they operate at different clock cycles in the second operating mode. 
   
   
       41 . The device as recited in  claim 35 , wherein the feed units are designed such that in the second operating mode they operate at a clock cycle that is twice as fast as that of the execution units. 
   
   
       42 . The device as recited in  claim 35 , further comprising:
 a decoder by which a switchover condition is detectable, wherein the decoder operates at the same clock cycle as the feed units.   
   
   
       43 . The device as recited in  claim 35 , further comprising:
 a comparison arrangement designed such that one of the operands and data derived from the operands are compared for agreement, wherein an error is detected in case of a deviation.   
   
   
       44 . The device as recited in  claim 35 , further comprising:
 a comparison arrangement designed such that states produced in the processing of the operands are compared for agreement, wherein an error is detected in case of a deviation.   
   
   
       45 . The device as recited in  claim 35 , further comprising:
 a first switching arrangement for switching the operands from the feed units as a function of one of the first operating mode and the second operating mode.   
   
   
       46 . The device as recited in  claim 45 , further comprising:
 a second switching arrangement for activating the execution units as a function of one of the first operating mode and the second operating mode.   
   
   
       47 . A processing unit, comprising:
 a device for operand processing having at least two execution units that are able to be operated at a predefinable clock cycle; and   a control unit for triggers the execution units by control signals for the processing of the operands and for switching between a first operating mode and a second operating mode,
 wherein:
 the control unit is connected to the execution units and additional feed units, 
 the control unit cooperates with the feed units in such a way that both execution units are supplied with the same operands in the first operating mode and both execution units are supplied with different operands in the second operating mode, and 
 the control unit being designed such that in the first operating mode both execution units are triggered by the same control signals for the processing of the operands and in the second operating mode both execution units are triggered by different control signals for the processing of the operands.