Flip-Chip Ball Grid Array Strip and Package

Abstract

The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. The use of a retention wall of a stiffener layer over an expensive substrate layer allows for the use of disposable edges around the strip including indexing holes or other holding mechanisms. What is also contemplated is a method of manufacture of a compact strip, matrix, or array comprised of a plurality of integrated circuit packages where no waste or additional cuts are needed to produce individual integrated circuit packages.

1 . An integrated circuit package, comprising:
 a substrate with a first surface and a second surface in opposition to the first surface;   an encapsulant retention structure coupled to the first surface;   a packaged integrated chip positioned adjacent to the encapsulant retention structure; and   an encapsulant interposed between at least a portion of the packaged integrated chip and the encapsulant retention structure and in contact with the encapsulant retention structure, wherein the encapsulant retention structure acts as a stiffener to minimize package warpage.   
   
   
       2 . (canceled) 
   
   
       3 . The integrated circuit package of  claim 1 , wherein the stiffener is comprised of a epoxy resin reinforced with a woven fiberglass mat. 
   
   
       4 . The integrated circuit package of  claim 1 , wherein the packaged integrated chip comprises a side wall and where the encapsulant is in contact with the side wall and the encapsulant retention structure. 
   
   
       5 . The integrated circuit package of  claim 1 , wherein the substrate has a thickness of about 70 to 400 microns. 
   
   
       6 . The integrated circuit package of  claim 1 , wherein the substrate has a thickness of about 400 microns. 
   
   
       7 . The integrated circuit package of  claim 1 , wherein the substrate is a thin core substrate structure. 
   
   
       8 . The integrated circuit package of  claim 1 , wherein the substrate is a substrate structure with no core. 
   
   
       9 . The integrated circuit package of  claim 1 , wherein the substrate is a polyimide tape substrate. 
   
   
       10 . The integrated circuit package of  claim 1 , wherein the package insulated circuit is integrated in a flip-chip ball grid array. 
   
   
       11 . The integrated circuit package of  claim 1 , wherein the stiffener has a thickness of about 500 to 1000 microns. 
   
   
       12 . The integrated circuit package of  claim 11 , wherein the packaged integrated chip has a thickness greater than the thickness of the stiffener. 
   
   
       13 . The integrated circuit package of  claim 12 , wherein a heat sink is attached to a top side of the packaged integrated chip. 
   
   
       14 . An integrated circuit package, comprising:
 a substrate;   a packaged integrated chip coupled to the substrate;   at least one passive electronic component coupled to the substrate; and   a stiffener comprising a top surface and a bottom surface, the bottom surface coupled to the substrate and at least partly surrounding the at least one passive electronic component.   
   
   
       15 . The integrated circuit package of  claim 14 , wherein the bottom surface is recessed and houses the at least one passive electronic component. 
   
   
       16 . The integrated circuit package of  claim 14 , wherein the stiffener is comprised of a epoxy resin reinforced with a woven fiberglass mat. 
   
   
       17 . The integrated circuit package of  claim 14 , wherein the substrate has a thickness of about 70 to 400 microns. 
   
   
       18 . The integrated circuit package of  claim 14 , wherein the substrate has a thickness of about 400 microns. 
   
   
       19 . The integrated circuit package of  claim 14 , wherein the substrate is a thin core substrate structure. 
   
   
       20 . The integrated circuit package of  claim 14 , wherein the substrate is a substrate structure with no core. 
   
   
       21 . The integrated circuit package of  claim 14 , wherein the substrate is a polyimide tape substrate. 
   
   
       22 . The integrated circuit package of  claim 14 , wherein the package insulated circuit is integrated in a flip-chip ball grid array. 
   
   
       23 . The integrated circuit package of  claim 14 , wherein the stiffener has a thickness of about 500 to 1000 microns. 
   
   
       24 . The integrated circuit package of  claim 23 , wherein the packaged integrated chip has a thickness greater than the thickness of the stiffener. 
   
   
       25 . The integrated circuit package of  claim 24 , wherein a heat sink is attached to a top side of the packaged integrated chip. 
   
   
       26 . The integrated circuit package of  claim 14 , wherein the at least one passive electronic component is a capacitor. 
   
   
       27 - 28 . (canceled) 
   
   
       29 . The integrated circuit package strip of  claim 47 , wherein the strip is comprised of an array of 3-by-10 integrated circuit packages. 
   
   
       30 . The integrated circuit package strip of  claim 47 , wherein the strip further comprises an outer edge comprising indexing holes surrounding the plurality of integrated circuit packages. 
   
   
       31 - 32 . (canceled) 
   
   
       33 . The integrated circuit package strip of  claim 30 , wherein the substrate has a thickness of about 70 to 400 microns. 
   
   
       34 . The integrated circuit package strip of  claim 30 , wherein the substrate has a thickness of about 400 microns. 
   
   
       35 . The integrated circuit package strip of  claim 30 , wherein the substrate is a thin core substrate structure. 
   
   
       36 . The integrated circuit package strip of  claim 30 , wherein the substrate is a substrate structure with no core. 
   
   
       37 . The integrated circuit package strip of  claim 30 , wherein the substrate is a polyimide tape substrate. 
   
   
       38 . The integrated circuit package strip of  claim 30 , wherein the stiffener has a thickness of about 500 to 1000 microns. 
   
   
       39 - 44 . (canceled) 
   
   
       45 . (canceled) 
   
   
       46 . The integrated circuit package of  claim 14 , comprising an encapsulant interposed between at least a portion of the packaged integrated chip and the stiffener and in contact with the stiffener. 
   
   
       47 . An integrated circuit package strip, comprising:
 a plurality of integrated circuit packages, wherein at least one integrated circuit package in the strip has four lateral sections and where the integrated circuit package shares at least two of the four lateral sections with different integrated circuit packages along the strip.   
   
   
       48 . A method of making an integrated circuit package strip, comprising:
 attaching an encapsulant retention structure having a plurality of openings each adapted to receive an integrated circuit chip to a substrate;   placing the integrated circuit chip in each of the plurality of openings;   placing an encapsulant between a side wall of the integrated circuit chip and the encapsulant retention structure and in contact with the encapsulant retention structure; and   curing the encapsulant.   
   
   
       49 . The method of making an integrated circuit package strip of  claim 48 , wherein the encapsulant is placed in a single operation. 
   
   
       50 . The integrated circuit package of  claim 1 , wherein the substrate and the encapsulant retention structure are made of the same material. 
   
   
       51 . (canceled)