High temperature operating package and circuit design

Abstract

The invention provides a semiconductor device that is thermally isolated from the printed circuit board such that the device operates at a higher temperature and radiates heat away from the printed circuit board. In another embodiment, the semiconductor is stacked onto a second device and optionally thermally isolated from the second device.

1 . A packaged semiconductor device, comprising:
 an encapsulant having a top surface and a bottom surface, said encapsulant comprising a thermally resistant material;   a die having a first surface and a second surface and being embedded in said encapsulant proximate to the top surface; and   a plurality of leads engaging said encapsulant proximate the bottom surface.   
   
   
       2 . The packaged semiconductor device of  claim 1 , further comprising a die pad embedded in the top surface of said encapsulant, said die pad having a die attach surface in engagement with the second surface of said die. 
   
   
       3 . The packaged semiconductor device of  claim 2 , said die pad comprising at least one surface that is exposed by said encapsulant. 
   
   
       4 . The packaged semiconductor device of  claim 2 , the die attach surface of said die pad being in electrical communication with the second surface of said die. 
   
   
       5 . The packaged semiconductor device of  claim 4 , said die being a field effect transistor and having one or more drain terminals on the second surface. 
   
   
       6 . The packaged semiconductor device of  claim 4 , one or more of said leads being in electrical communication with the die attach surface of said die pad via a bond wire. 
   
   
       7 . The packaged semiconductor device of  claim 1 , each of said leads being in electrical communication with a terminal on said die via a bond wire. 
   
   
       8 . The packaged semiconductor device of  claim 1 , wherein said die is a field effect transistor. 
   
   
       9 . The packaged semiconductor device of  claim 1 , wherein said die is an integrated circuit. 
   
   
       10 . The packaged semiconductor device of  claim 1 , wherein said die is comprised of silicon carbide. 
   
   
       11 . The packaged semiconductor device of  claim 1 , wherein said leads are connected to a printed circuit board such that the bottom surface of said encapsulant is proximate the printed circuit board. 
   
   
       12 . A method of forming a package for a semiconductor device having a high temperature operation, comprising the steps of:
 providing a semiconductor die attached to a die pad and vertically displaced from a plurality of leads;   electrically connecting each of said leads to a terminal on said die via bond wires;   encapsulating the die, the bond wires, at least a portion of the die pad, and at least a portion of the leads in a thermally resistant material; and   attaching the leads to a circuit such that the die and the die pad are displaced from the circuit and substantially thermally isolated from the circuit.   
   
   
       13 . The method of  claim 12 , the circuit comprising a printed circuit board. 
   
   
       14 . The method of  claim 12 , the die being a field effect transistor having a drain terminal in electrical communication with the die pad. 
   
   
       15 . The method of  claim 12 , the die being an integrated circuit. 
   
   
       16 . The method of  claim 12 , the die comprising silicon carbide. 
   
   
       17 . A circuit having a thermally isolated semiconductor device, the circuit comprising:
 a first semiconductor die having a first die top surface and a first die bottom surface;   a second semiconductor die having a second die top surface and a second die bottom surface, the first die bottom surface being attached to the second die top surface;   a thermal resistance layer situated between said first die and said second die; and   a die pad having a die attach surface engaging the second die bottom surface.   
   
   
       18 . The circuit of  claim 17 , at least one of said first die and said second die being an integrated circuit. 
   
   
       19 . The circuit of  claim 17 , each of said first die and said second die being a field effect transistor wherein:
 said first die comprises a first die source terminal and a first die gate terminal on the first die top surface and a first die drain terminal on the first die bottom surface; and   said second die comprising a second die source terminal and a second die gate terminal on the second die top surface and a second die drain terminal on the second die bottom surface.   
   
   
       20 . The circuit of  claim 19 , the thermal resistance layer being electrically conductive such that the first die drain terminal is in electrical communication with the second die source terminal to connect said first die and said second die in series. 
   
   
       21 . The circuit of  claim 20 , the first die gate terminal and the second die gate terminal being in electrical communication with a common gate drive. 
   
   
       22 . The circuit of  claim 21 , said second die having a lower threshold voltage than said first die. 
   
   
       23 . The circuit of  claim 21 , the first die source terminal being in electrical communication with a lead and the second die drain terminal being in electrical communication with said die pad. 
   
   
       24 . The circuit of  claim 20 , the first die gate terminal and the second die gate terminal being electrically connected to a gate timing circuit for controlling the activation and the deactivation of said first die and said second die. 
   
   
       25 . The circuit of  claim 20 , the thermal resistance layer being an electrically conductive epoxy. 
   
   
       26 . The circuit of  claim 20 , the thermal resistance layer being a tungsten layer. 
   
   
       27 . The circuit of  claim 17 , said first die comprising silicon carbide. 
   
   
       28 . The circuit of  claim 27 , said second die comprising silicon. 
   
   
       29 . A method of providing a semiconductor power device with current leakage prevention, comprising the steps of:
 providing a first field effect transistor (FET) die with a first FET gate terminal and a first FET source terminal on a first FET top surface and a first FET drain terminal on a first FET bottom surface;   providing a second FET die with a second FET gate terminal and a second FET source terminal on a second FET top surface and a second FET drain terminal on a second FET bottom surface, wherein the second FET has a lower threshold voltage that the first FET;   attaching the first FET die to the second FET die with an electrically conductive thermal resistance layer therebetween such that the first FET drain terminal is in electrical communication with the second FET source terminal; and   affixing the second FET die to a die pad.   
   
   
       30 . The method of  claim 29 , further comprising the step of connecting the first FET gate terminal and the second FET gate terminal to a common gate drive. 
   
   
       31 . The method of  claim 29 , the first FET die comprising silicon carbide and the second FET die comprising silicon. 
   
   
       32 . The method of  claim 29 , the thermal resistance layer comprising a material selected from the group consisting essentially of an electrically conductive epoxy and a tungsten layer. 
   
   
       33 . A circuit comprising a plurality of semiconductor power devices configured in a stack and connected in series. 
   
   
       34 . The circuit of  claim 33 , further comprising a thermal resistance layer between at least two of said plurality of semiconductor power devices. 
   
   
       35 . The circuit of  claim 33 , wherein one or more of said semiconductor power devices are field effect transistors. 
   
   
       36 . The circuit of  claim 33 , wherein one or more of said semiconductor power devices comprise silicon carbide.