Leakage improvement for a high-voltage latch

Abstract

An improved CMOS high-voltage latch stores data bits to be written to memory cells of a non-volatile memory has two cross-coupled CMOS inverters. One of the inverters has a pull-down leg that includes a pass-gate high-voltage NMOS transistor that is connected between a latch output node and a second high-voltage, low-threshold NMOS pull-down transistor that is connected to ground. A gate of the pass-gate high-voltage NMOS transistor receives a standby signal with a logic HIGH value of at most Vdd to turn on the pass-gate high-voltage NMOS transistor when the high-voltage CMOS latch is in a voltage mode of operation and during a high-voltage write mode of operation. The pass-gate high-voltage NMOS transistor thereby limits the voltage across the second high-voltage, low-threshold NMOS pull-down transistor to less than the standby signal in order to reduce punch-trough current and drain-to-substrate leakage of the second high-voltage, low-threshold NMOS pull-down transistor.

1 . A non-volatile memory having a plurality of high-voltage CMOS latches, each high-voltage CMOS latch comprising:
 a HV terminal that is connected to a VDD supply voltage during a standby mode of operation and during a load data mode of operation and that is connected to a HIGH-VOLTAGE supply voltage during a high-voltage write mode of operation;   a first CMOS inverter and a second CMOS inverter, each having respective input and output terminals, and each being connected between the HV terminal and a ground terminal;   the input terminal of the second CMOS inverter and the output terminal of the first CMOS inverter are connected to a latch input node A;   the input terminal of the first CMOS inverter and the output terminal of the second CMOS output terminal are connected to a latch output node B;   said first CMOS inverter having a first PMOS pull-up transistor connected between the HV terminal and the latch input node A, said first CMOS inverter having a first NMOS pull-down transistor connected between the latch input node A and the ground terminal;   said second CMOS inverter having a second PMOS pull-up transistor connected between the HV terminal and the latch output node B;   said second CMOS inverter having a pass-gate high-voltage NMOS transistor that is connected between the latch output node B and a second high-voltage, low-threshold NMOS pull-down transistor that is connected to the ground terminal; and   said pass-gate high-voltage NMOS transistor having a gate connected to a STANDBY terminal that receives a HIGH LOGIC signal with a value of at most VDD to turn on the pass-gate high-voltage NMOS transistor when the high-voltage CMOS latch is in a data-loading mode of operation and during a high-voltage write mode of operation to limit the voltage across the second high-voltage, low-threshold NMOS pull-down transistor and to reduce punch-through current and drain-to-substrate leakage of the second high-voltage, low-threshold NMOS pull-down transistor.   
   
   
       2 . The non-volatile memory of  claim 1  wherein each high-voltage CMOS latch circuit has a DATA IN input terminal connected to the latch input node A through a load input NMOS transistor, at a gate terminal of which is provided a DATA LOAD signal to turn on the NMOS load input NMOS transistor. 
   
   
       3 . The non-volatile memory of  claim 1  including a reset NMOS transistor that is connected between the latch input node A and the ground terminal and that has a gate terminal at which is provided a HIGH RESET signal to turn on the reset NMOS transistor during the standby mode of operation and at which is provided a LOW RESET signal to turn off the reset NMOS transistor during a data-loading mode of operation and during a high-voltage write mode of operation. 
   
   
       4 . A method limiting leakage current in one or more high-voltage latches that are used for high-voltage writing of data into a non-volatile memory, comprising the steps for each of the one or more latches of:
 connecting a cross-coupled CMOS latch between a HV terminal and a ground terminal by connecting a first CMOS inverter between a HV terminal and a ground terminal and by connecting a second high-voltage inverter between the HV terminal and a ground terminal;   connecting an input terminal of the second CMOS inverter and an output terminal of the first CMOS to a latch input node A for the latch circuit;   connecting the latch input node A through a NMOS load input NMOS transistor to a DATA In input terminal of the latch;   providing a LOAD signal at a gate terminal of the NMOS load input NMOS transistor to turn on the NMOS load input NMOS transistor;   connecting an input terminal of the first CMOS inverter and an output terminal of the second CMOS output terminal to a latch output node B for the latch circuit;   connecting a high-voltage, pass-gate NMOS transistor between the latch output node A and one terminal of a low-threshold NMOS pull-down transistor that has another terminal connected to ground; and   limiting the voltage across the second high-voltage, low threshold NMOS pull-down transistor and the reducing punch through current and drain-to substrate leakage by turning on the pass-gate high-voltage NMOS transistor with a HIGH signal with a value of Vdd at most.   
   
   
       5 . A latch circuit, comprising:
 first and second cross-coupled inverters, each inverter having a PMOS transistor connected to a supply voltage and an NMOS transistor connected to ground with the gates of the EMOS and NMOS transistors joined at a first node and with a second node joining source-drains thereof, with the first node of the first inverter connected to the second node of the second inverter, with the second node of the first inverter connected to the first node of the second inverter and to a transistor means for applying a RESET voltage; and   a pass-gate transistor means interposed between the PMOS and the NMOS transistors of the second inverter for applying a STANDBY voltage to the NMOS transistor of the second inverter to thereby limit the voltage at the NMOS transistor to the voltage established by the STANDBY voltage.   
   
   
       6 . The latch circuit of  claim 5  having means for operating in three modes, a first mode being a STANDBY mode, a second mode being a LOAD DATA mode, and a third mode being a WRITE mode. 
   
   
       7 . The latch circuit of  claim 6  wherein the supply voltage supplies a second voltage Vdd lower than the high voltage, the Vdd voltage being connected to the latch circuit during the first and second modes of operation and the high voltage connected to the latch circuit during the third mode of operation. 
   
   
       8 . The latch circuit of  claim 6  wherein the first and second inverters have PMOS pull-up transistors and wherein the first inverter has an NMOS pull-down transistor and the second inverter has an NMOS pass-gate transistor that is in series with an NMOS pull-down transistor and that is inactive in the first mode and active in the second and third modes. 
   
   
       9 . The latch circuit of  claim 5  having a first auxiliary transistor associated with a DATA TN terminal and a DATA LOAD signal terminal, the auxiliary transistor connected to the second node of the first inverter and to the first node of the second inverter. 
   
   
       10 . The latch circuit of  claim 9  wherein the auxiliary transistor is an NMOS transistor. 
   
   
       11 . The latch circuit of  claim 9  wherein a second auxiliary transistor means for applying a RESET voltage is connected to the second node of the first inverter and the first node of the second inverter. 
   
   
       12 . A method of operating a latch circuit in association with a programmable memory device comprising,
 connecting first and second CMOS inverters with PMOS and NMOS transistors in a manner forming a cross-coupled CMOS latch between a high voltage terminal and a ground terminal;   providing a high voltage for writing to a high voltage device in a write mode;   providing a lower voltage than the high voltage for loading data into the CMOS latch in a LOAD DATA mode and during a STANDBY mode; and   providing a pass-gate transistor in series with one of said CMOS inverters for applying a STANDBY voltage to turn on the pass-gate transistor and thereby limit voltage across an NMOS transistor in the one of said CMOS inverters.   
   
   
       13 . The method of  claim 12  including providing a first auxiliary transistor to the CMOS latch for establishing a DATA LOAD signal. 
   
   
       14 . The method of  claim 12  including providing a second auxiliary transistor to the latch for establishing a RESET sigral. 
   
   
       15 . The method of  claim 12  including providing a low threshold NNOS pull-down transistor in series with the pass-gate transistor that limits voltage across the low threshold NMOS pull-down transistor. 
   
   
       16 . The method of  claim 12  including connecting the CMOS inverters with an input terminal of the second CMOS inverter and an output terminal of the first CMOS inverter to a latch input node and connecting the input terminal of the first CMOS inverter and an output terminal of the second CMOS inverter to a latch output node.