Semiconductor Device

Abstract

In an n-channel type power MISFET, a source electrode in contact with an n + -semiconductor region (source region) and a p + -semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of MoSi 2 , use of the material having higher barrier height relation to n-Si for the barrier film increasing the contact resistance to n-Si and backwardly biasing the emitter and base of a parasitic bipolar transistor making it less tending to turn-on, thereby decreasing the leak current of power MISFET.

1 - 37 . (canceled)  
   
   
       38 . A method of manufacturing a semiconductor device having a trench gate type MISFET, comprising the steps of: 
 (a) providing a semiconductor substrate with a semiconductor layer formed over a main surface of said semiconductor substrate;    (b) forming a plurality of gate trenches of the MISFET on a main surface of the semiconductor layer;    (c) forming a plurality of gate dielectric films in the gate trenches respectively;    (d) forming a plurality of gate portions on the gate dielectric films respectively;    (e) forming a plurality of channel regions of the MISFET, in the semiconductor layer, between adjacent gate portions respectively;    (f) forming a plurality of source regions of the MISFET, in the semiconductor layer, over the channel regions respectively;    (g) forming an insulating film over the source regions and gate portions;    (h) forming a plurality of contact trenches, in the insulating film and semiconductor layer, to expose the source regions and channel regions;    (i) forming a first conductive film in the contact trenches to contact with the source regions and channel regions; and    (j) forming a source electrode on the barrier film,    wherein the semiconductor substrate, semiconductor layer and source regions have a first conduction type;    wherein the channel regions have a second conduction type;    wherein the source electrode is comprised of a second conductive film; and    wherein the first conductive film and the source electrode are formed such that a parasitic bipolar transistor, which provides a leakage current path between one of the source regions and a drain region of the MISFET, takes an off-state under a predetermined condition which would otherwise cause said parasitic bipolar transistor to take an on-state.    
   
   
       39 . A method of manufacturing a semiconductor device according to  claim 38 , wherein said predetermined condition is a condition in which a voltage is applied to said drain region and a voltage between said one source region and a respective gate region is zero.  
   
   
       40 . A method of manufacturing a semiconductor device according to  claim 38 , wherein a material of the first conductive film is selected to provide a barrier height, with respect to a material of the semiconductor layer, which is effective to cause the parasitic bipolar transistor to take the off-state.  
   
   
       41 . A method of manufacturing a semiconductor device according to  claim 40 , wherein said barrier height is provided by a reaction product of the material of the first conductive film and a material of the second conductive film.  
   
   
       42 . A method of manufacturing a semiconductor device according to  claim 38 , wherein the parasitic bipolar transistor has an emitter region corresponding to said one source region of the MISFET, a base region corresponding to a respective channel region of the MISFET, and a collector region corresponding to said drain region of the MISFET.  
   
   
       43 . A method of manufacturing a semiconductor device according to  claim 38 , wherein the insulating film comprises a silicon oxide film.  
   
   
       44 . A method of manufacturing a semiconductor device according to  claim 38 , wherein the semiconductor layer comprises an epitaxial film.  
   
   
       45 . A method of manufacturing a semiconductor device according to  claim 44 , wherein the epitaxial film is a silicon film.  
   
   
       46 . A method of manufacturing a semiconductor device according to  claim 45 , wherein the epitaxial silicon film is a single crystal silicon film.  
   
   
       47 . A method of manufacturing a semiconductor device according to  claim 38 , wherein the second conductive film comprises aluminum.  
   
   
       48 . A method for manufacturing a semiconductor device according to  claim 40 , wherein the first conduction type is n-type, the second conduction type is p-type, and said first conductive film is mainly comprised of a material selected from the group consisting of Co, Ni, Rh, Mo, Pb, Mn, Pt, Ir, and combinations thereof.  
   
   
       49 . A method of manufacturing a semiconductor device according to  claim 40 , wherein the first conduction type is p-type, the second conduction type is n-type, and said first conductive film is mainly comprised of a material selected from the group consisting of Co, Ti, Ta, Cr, Mo, Zr, Hf, and combinations thereof.  
   
   
       50 . A method of manufacturing a semiconductor device according to  claim 38 , wherein a diameter of the contact trench formed in the insulating film is larger than that of the contact trench formed in the semiconductor layer.  
   
   
       51 . A method of manufacturing a semiconductor device according to  claim 38 , wherein the first conductive film and the source electrode are formed by a sputtering method in the steps (i) and (j), respectively.  
   
   
       52 . A method of manufacturing a semiconductor device according to  claim 38 , further comprising the step of: 
 (k) forming a drain electrode on a rear surface of the semiconductor substrate.    
   
   
       53 . A method of manufacturing a semiconductor device according to  claim 38 , further comprising the step of: 
 (l) between the steps (h) and (i), forming a back gate contact region under a bottom of each of the contact trenches so as to contact with the bottom of each of the contact trenches,    wherein the back gate contact region has the second conduction type;    an impurity concentration of the back gate contact region is higher than that of the respective channel region; and    the source electrode is electrically connected with the back gate contact region.    
   
   
       54 . A method of manufacturing a semiconductor device according to  claim 38 , 
 wherein the plurality of gate trenches are integrally formed;    the plurality of gate portions are integrally formed; and    the plurality of source regions are electrically connected.