US2008061298A1PendingUtilityA1

Semiconductor element and semiconductor memory device using the same

Assignee: YANO KAZUOPriority: Aug 19, 1993Filed: Oct 31, 2007Published: Mar 13, 2008
Est. expiryAug 19, 2013(expired)· nominal 20-yr term from priority
H10D 86/201H10D 30/62H10D 88/01H10D 88/00H10D 84/038H10D 64/685H10D 30/6892H10D 30/688H10D 30/0411H10D 30/402H10D 64/035G11C 16/10G11C 2216/08G11C 11/404G11C 2216/06G11C 16/28B82Y 10/00G11C 16/0466G11C 11/22G11C 16/02H10B 41/49H10B 69/00H10B 41/40H10B 41/20H10B 12/00
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Claims

Abstract

A semiconductor memory device includes a plurality of memory cells, each including, a source region formed of a semiconductor material, a drain region formed of the semiconductor material, and a first region formed of the semiconductor material and located between the source region and the drain region. First and second insulator films sandwich the first region and a first gate electrode is connected to the first region through the first insulator film. In this arrangement, the first region is adapted to accumulate charges corresponding to stored information.

Claims

exact text as granted — not AI-modified
1 . A semiconductor memory device comprising: 
 a plurality of memory cells, each of the plurality of memory cells including, 
 a source region formed of a semiconductor material;  
 a drain region formed of the semiconductor material;  
 a first region formed of the semiconductor material and located between the source region and the drain region;  
 first and second insulator films, the first region being sandwiched between the first and second insulator films; and  
 a first gate electrode connected to the first region through the first insulator film,  
   wherein the first region is adapted to accumulate charges corresponding to stored information.    
     
     
         2 . A semiconductor memory device according to  claim 1 , further comprising: 
 a second gate electrode connected to the first region through the second insulator film.    
     
     
         3 . A semiconductor memory device according to  claim 1 , 
 wherein a thickness of the source region is larger than a thickness of the first region, and    wherein a thickness of the drain region is larger than a thickness of the first region.    
     
     
         4 . A semiconductor memory device according to  claim 1 , further comprising: 
 a plurality of word lines coupled to the first gate electrodes of the plurality of memory cells; and    a plurality of data lines coupled to the drain regions of the plurality of memory cells and crossing the plurality of word lines,    wherein the plurality of memory cells are arranged in a reticular pattern.

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