Method and apparatus for generating a clock signal and for controlling a clock frequency using the same

Abstract

A method and a device for generating a clock signal determine a number of pulses to be discarded from each predetermined cycle of a reference clock signal in order to obtain, on average, a target frequency. A masking pattern is created for discarding the number of pulses to be discarded from each predetermined cycle of the reference clock signal. The clock signal, which includes the target frequency, is generated by discarding the number of pulses from the reference clock signal using the masking pattern.

1 . A method of generating a clock signal, the method comprising:
 determining a number of pulses to be discarded from each predetermined cycle of a reference clock signal in order to obtain, on average, a target frequency;   creating a masking pattern for discarding the number of pulses to be discarded from each predetermined cycle of the reference clock signal; and   generating the clock signal, comprising the target frequency, by discarding the number of pulses from the reference clock signal using the masking pattern.   
   
   
       2 . The method of  claim 1 , wherein determining the number of pulses to be discarded comprises:
 obtaining a greatest common divisor (G.C.D.) of a frequency of the reference clock signal and the target frequency;   dividing each of the reference clock signal frequency and the target frequency by the G.C.D.; and   determining a length of the predetermined cycle to include pulses of the reference clock signal, a number of the pulses being equal a value obtained by dividing the reference clock signal frequency by the G.C.D.;   the number of pulses to be discarded comprising a difference between the value obtained by dividing the reference clock signal frequency by the G.C.D. and a value obtained by dividing the target frequency by the G.C.D.   
   
   
       3 . The method of  claim 1 , further comprising:
 changing a location of at least one clock pulse to be discarded from each predetermined cycle, according to an initial set, using the masking pattern.   
   
   
       4 . A method of generating a target clock signal, the method comprising:
 calculating a pulse detecting location in a cycle, the cycle comprising a number of pulses corresponding to an inverse of a frequency of the target clock signal;   detecting a pulse of a reference clock signal, the detected pulse having a predetermined relationship with the calculated pulse detecting location; and   generating the target clock signal using the detected pulse of the reference clock signal.   
   
   
       5 . The method of  claim 4 , wherein the detected pulse of the reference clock signal comprises a closest pulse to the calculated pulse detecting location. 
   
   
       6 . The method of  claim 4 , wherein the detected pulse of the reference clock signal comprises a pulse generated immediately before the calculated pulse detecting location. 
   
   
       7 . The method of  claim 4 , wherein the detected pulse of the reference clock signal comprises a pulse generated immediately after the calculated pulse detecting location. 
   
   
       8 . The method of  claim 4 , wherein the detected pulse of the reference clock signal comprises a pulse generated an initially set number of pulses after the calculated pulse detecting location. 
   
   
       9 . The method of  claim 4 , further comprising:
 changing a duty ratio of the generated target clock signal to comply with an initially set standard.   
   
   
       10 . A method of generating a target clock signal, the method comprising:
 receiving an externally provided clock signal for detecting a pulse, the clock signal having a target frequency;   detecting a pulse of a reference clock signal in relation to a pulse occurrence location of the clock signal for detecting a pulse; and   generating the target clock signal using the detected pulse of the reference clock signal.   
   
   
       11 . The method of  claim 10 , wherein the detected pulse of the reference clock signal comprises a pulse generated immediately after the calculated pulse detecting location. 
   
   
       12 . The method of  claim 10 , wherein the detected pulse of the reference clock signal comprises a pulse generated an initially set number of pulses after the calculated pulse detecting location. 
   
   
       13 . The method of  claim 10 , further comprising:
 changing a duty of the generated target clock signal to comply with an initially set standard.   
   
   
       14 . A method of controlling a clock frequency, the method comprising:
 generating a clock signal for an application having, on average, a target frequency from a reference clock signal;   calculating a data processing progress percentage of processing data using the clock signal;   determining a difference between the calculated data processing progress percentage and a target progress percentage; and   changing the target frequency of the clock signal based on the determined difference.   
   
   
       15 . The method of  claim 14 , wherein generating the clock signal for the application comprises discarding a calculated number of pulses from each of a plurality of sections of the reference clock signal, so that the reference clock signal comprises, on average, the target frequency. 
   
   
       16 . The method of  claim 14 , wherein generating the clock signal for the application comprises:
 calculating a pulse detecting location in a plurality of cycles of the reference clock signal, a number of pulses of a cycle corresponding to an inverse of the target frequency; and   detecting a pulse of the reference clock signal closest to the calculated pulse detecting location.   
   
   
       17 . The method of  claim 14 , wherein changing the target frequency of the clock signal comprises:
 decreasing the target frequency of the clock signal when the calculated progress percentage is greater than the target progress percentage by a first predetermined amount; and   increasing the target frequency of the clock signal when the calculated progress percentage is less than the target progress percentage by a second predetermined amount.   
   
   
       18 . A device for generating a clock signal for an application, the device comprising:
 a reference clock generator configured to generate a reference clock signal comprising a plurality of clock pulses;   a masking pattern generator configured to create a masking pattern to discard at least one clock pulse of the plurality of clock pulses from the reference clock signal to generate a target frequency from the reference clock signal; and   an AND gate configured to generate the clock signal for the application by logically multiplying the reference clock signal and the masking pattern.   
   
   
       19 . The device of  claim 18 , wherein the masking pattern generator comprises:
 a counter configured to count a number of pulses of the reference clock signal; and   a mapping unit configured to output signals having logic values mapped to either 0 or 1, based on a ratio of the frequency of the reference clock signal to the target frequency.   
   
   
       20 . The device of  claim 19 , wherein the counter is further configured to count in units of N, where N comprises a value obtained by dividing the frequency of the reference clock signal by a greatest common devisor (G.C.D.) of the frequency of the reference clock signal and the target frequency 
   
   
       21 . A device for generating a clock signal for an application, the device comprising:
 a reference clock generator configured to generate a reference clock signal;   a microprocessor configured to calculate a pulse detecting location in a plurality of cycles, each cycle comprising a number of pulses corresponding to an inverse of a target frequency of a clock signal for an application; and   a pulse detector configured to generate the clock signal by detecting a pulse of the reference clock signal having a predetermined relationship with the pulse detecting location.   
   
   
       22 . The device of  claim 21 , wherein the pulse detector detects the pulse of the reference clock signal closest to the calculated pulse detecting location. 
   
   
       23 . The device of  claim 21 , wherein the pulse detector detects the pulse of the reference clock signal generated immediately before the calculated pulse detecting location. 
   
   
       24 . The device of  claim 21 , wherein the pulse detector detects the pulse of the reference clock signal generated immediately after the calculated pulse detecting location. 
   
   
       25 . The device of  claim 21 , wherein the pulse detector detects the pulse of the reference clock signal generated an initially set number of pulses after the calculated pulse detecting location. 
   
   
       26 . The device of  claim 21 , further comprising:
 a duty alteration circuit configured to change a duty of the clock signal output from the pulse detector to comply with an initially set standard.   
   
   
       27 . A device for controlling a clock frequency, the device comprising:
 a clock signal generating circuit configured to generate a clock signal for an application, the clock signal having a target frequency from a reference clock signal;   an application circuit configured to process data using the clock signal for the application; and   a microprocessor configured to calculate a data processing progress percentage of the application circuit and to control the clock signal generating circuit to change the target frequency based on a difference between the calculated data processing progress percentage and a target progress percentage.   
   
   
       28 . The device of  claim 27 , wherein the clock signal generating circuit comprises:
 a masking pattern generator configured to create a masking pattern to discard at least one pulse from the reference clock signal to obtain the target frequency from the reference clock signal; and   an AND gate configured to generate the clock signal for the application by logically multiplying the reference clock signal and the masking pattern.   
   
   
       29 . The device of  claim 27 , wherein the clock signal generating circuit comprises:
 an arithmetic circuit configured to calculate a pulse detecting location in a plurality of cycles, each cycle comprising a number of pulses corresponding to an inverse of the target frequency of the clock signal for the application; and   a pulse detector configured to detect a pulse of the reference clock signal generated closest to the pulse detecting location.   
   
   
       30 . The device of  claim 27 , wherein the microprocessor is further configured to control the clock signal generating circuit to decrease a frequency of the clock signal when the calculated progress percentage is greater than the target progress percentage by a first predetermined amount, and to increase the frequency of the clock signal when the calculated progress percentage is less than the target progress percent by a second predetermined amount.